Patents by Inventor Chuan Wang

Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CARRIER AGGREGATION LOW-NOISE AMPLIFIER WITH TUNABLE INTEGRATED POWER SPLITTER
    Publication number: 20170201218
    Abstract: A device includes a low-noise amplifier (LNA) and a matching circuit. The matching circuit is coupled to an output of the LNA and switchably coupled to at least one of a first and a second output of the device. The device may further include a power splitter switchably coupled between an output of the matching circuit and the first and/or the second output of the device.
    Type: Application
    Filed: June 9, 2016
    Publication date: July 13, 2017
    Inventors: Chuan WANG, Kevin Hsi Huai WANG, Chiewcharn NARATHONG, Mehmet UZUNKOL, Prakash THOPPAY EGAMBARAM
  • Semiconductor wafer probing system including pressure sensing and control unit
    Patent number: 9702930
    Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
  • VERIFICATION APPARATUS AND VERIFICATION METHOD FOR TOUCH DISPLAY PANEL
    Publication number: 20170192606
    Abstract: A verification apparatus and a verification method are provided in this disclosure. The verification apparatus is suitable for touch display panel which comprises multiple partitions. The verification apparatus includes signal generating circuit and verification switch circuit. The signal generating circuit is configured to generate verification voltage. The verification switch circuit comprises multiple switch units which is separately coupled to the partitions and the signal generating circuit, and is configured to deliver verification voltage simultaneously to a least two of multiple partitions.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 6, 2017
    Inventors: Shao-Lun CHANG, Chang-Sheng WENG, Chi-Liang KUO, Wen-Chuan WANG
  • DRIVING CIRCUIT AND DRIVING METHOD
    Publication number: 20170193957
    Abstract: A driving circuit in this disclosure includes plural stages of shift register circuits. Every stage in the shift register circuits includes an enabling control circuit, a first output circuit, a second output circuit and a disabling control circuit. The enabling circuit is configured to control the voltage of the first operation node according to enabling signal. The first output unit is configured to generate the first driving signal according to the voltage of the first operation node and the first clock signal. The second output unit is configured to generate the second driving signal according to the voltage of the first operation node and the second clock signal. The disabling control unit is used to pull low the voltage of the first operation node and output terminal of the first and second output unit to the reference voltage according to the first, third, and fourth clock signals.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 6, 2017
    Inventors: Han-Lung LIU, Wei-Lien SUNG, Wen-Chuan WANG, Shao-Lun CHANG, Shih-Chieh LIN
  • IP ADDRESS AND DOMAIN NAME AUTOMATION OF VIRTUAL INFRASTRUCTURE
    Publication number: 20170187677
    Abstract: Provisioning an Internet Protocol address is disclosed. A request to provision an Internet Protocol address to a virtual resource is received. An Internet Protocol address is automatically determined to allocate to the virtual resource. The determined Internet Protocol address was selected from a group of Internet Protocol addresses potentially available to be assigned to the virtual resource of the received request.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Soheil Eizadi, Steven Whittle, Chuan Wang
  • AMPLIFIER WITH COUPLED INDUCTORS
    Publication number: 20170187338
    Abstract: An apparatus includes an inductor device including a first inductor coupled to a second inductor. The first inductor and the second inductor are connected to ground. A first transistor and a second transistor are coupled to the inductor device. A first cascode transistor is coupled to the first transistor, and a second cascode transistor is coupled to the second transistor. The first cascode transistor is coupled to a first output, and the second cascode transistor is coupled to a second output.
    Type: Application
    Filed: June 21, 2016
    Publication date: June 29, 2017
    Inventors: Chuan Wang, Kevin Hsi Huai Wang, Xinhua Chen, Mehmet Uzunkol
  • METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY
    Publication number: 20170186584
    Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.
    Type: Application
    Filed: January 23, 2017
    Publication date: June 29, 2017
    Inventors: Jyuh-Fuh LIN, Cheng-Hung CHEN, Pei-Yi LIU, Wen-Chuan WANG, Shy-Jay LIN, Burn Jeng LIN
  • On-chip semiconductor device having enhanced variability
    Patent number: 9691718
    Abstract: A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Method of Fabricating an Integrated Circuit With Non-Printable Dummy Features
    Publication number: 20170176849
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 22, 2017
    Inventors: JYUH-FUH LIN, CHENG-HUNG CHEN, PEI-YI LIU, WEN-CHUAN WANG, SHY-JAY LIN, BURN JENG LIN
  • Grid refinement method
    Patent number: 9678434
    Abstract: Lithography methods disclosed herein accommodate shrinking pattern dimensions. An exemplary method includes receiving a pattern to be transferred to a workpiece by a pattern generator. The pattern generator is divided into a first segment set and a second segment set based on the pattern, such that a collective exposure dose from the first segment set and the second segment set satisfies an exposure dose specified by the pattern. The first segment set is offset from the second segment set in a first direction, and segments in the first segment set and segments in the second segment set are offset from each other in a second direction different than the first direction. The method further includes exposing the workpiece according to the first segment set and the second segment set.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Burn Jeng Lin, Jaw-Jung Shin, Pei-Yi Liu, Shy-Jay Lin
  • METHOD FOR PREPARING A SODIUM FAUJASITE CATALYST AND ITS USE IN PRODUCING ACRYLIC ACID
    Publication number: 20170157597
    Abstract: The invention relates generally to a sodium faujasite catalyst, and in particular the use of the sodium faujasite catalyst in producing acrylic acid. In particular, the invention relates to the use of the sodium faujasite catalyst in catalytic dehydration of lactic acid and 3-hydroxypropionic acid (3-HP) to produce acrylic acid.
    Type: Application
    Filed: March 26, 2015
    Publication date: June 8, 2017
    Inventors: Chuan Wang, Zhen Guo, Armando Borgna
  • LENS MODULE AND IMAGE APPARATUS
    Publication number: 20170160525
    Abstract: A lens module for capturing an object light-beam from an object-side is provided. The lens module includes a first lens group, a second lens group, a third lens group, a fourth lens group and a fifth lens group sequentially-arranged from the object-side to an image-side. The five lens groups respectively have at least one lens with positive refractive-power and at least one lens with negative refractive-power. The first, third and fifth lens groups are fixed groups, while the second and fourth lens groups are movable groups. An image apparatus including the lens module is also provided.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Applicant: Young Optics Inc.
    Inventors: Kuo-Chuan Wang, Sheng-Tang Lai
  • Interconnect structure with enhanced reliability
    Patent number: 9673089
    Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 6, 2017
    Assignee: AURIGA INNOVATIONS, INC
    Inventors: Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Ronald G. Filippi, Andrew H. Simon, Ping-Chuan Wang
  • System and technique for rasterizing circuit layout data
    Patent number: 9658538
    Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Yi Liu, Cheng-Chi Wu, Cheng-Hung Chen, Jyuh-Fuh Lin, Wen-Chuan Wang, Shy-Jay Lin
  • ON-CHIP RANDOMNESS GENERATION
    Publication number: 20170141771
    Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
  • Current limiting device, current limiter and current limiting system for power grid
    Patent number: 9640984
    Abstract: A current limiting device for a power grid includes a first current limiting reactor; a first smart fast switch connected with the first current limiting reactor in parallel; a current transformer sleeved on a bus bar located on one side of a circuit resulting from the parallel connection of the first current limiting reactor with the first smart fast switch to monitor the current in the bus bar in real time; and a controller connected with the current transformer to control the switch-off of the first smart fast switch when the current in the bus bar is higher than a first preset value and the switch-on of the first smart fast switch when the current in the bus bar is smaller than a second preset value, wherein the first preset value is higher than the second preset value. The current limiting device improves the operational reliability of a power grid.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: May 2, 2017
    Assignees: STATE GRID NINGXIA ELECTRIC POWER TECHNICAL RESEARCH INSTITUTE, ANHUI HUIDIAN SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Shaogui Al, Chuan Wang, Yongning Huang, Yiping Fan, Guoyong Zhang, Yanjun Li, Ning Pan, Shuang Zhang
  • IP address and domain name automation of virtual infrastructure
    Patent number: 9634983
    Abstract: Provisioning an Internet Protocol address is disclosed. A request to provision an Internet Protocol address to a virtual resource is received. An Internet Protocol address is automatically determined to allocate to the virtual resource. An Internet Protocol Address Management appliance is used to automatically allocate the determined Internet Protocol address to the virtual resource.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: April 25, 2017
    Assignee: Infoblox Inc.
    Inventors: Soheil Eizadi, Steven Whittle, Chuan Wang
  • GRID REFINEMENT METHOD
    Publication number: 20170102624
    Abstract: Lithography methods disclosed herein accommodate shrinking pattern dimensions. An exemplary method includes receiving a pattern to be transferred to a workpiece by a pattern generator. The pattern generator is divided into a first segment set and a second segment set based on the pattern, such that a collective exposure dose from the first segment set and the second segment set satisfies an exposure dose specified by the pattern. The first segment set is offset from the second segment set in a first direction, and segments in the first segment set and segments in the second segment set are offset from each other in a second direction different than the first direction. The method further includes exposing the workpiece according to the first segment set and the second segment set.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: Wen-Chuan Wang, Burn Jeng Lin, Jaw-Jung Shin, Pei-Yi Liu, Shy-Jay Lin
  • WAFER REINFORCEMENT TO REDUCE WAFER CURVATURE
    Publication number: 20170098616
    Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
  • Wireless charging system and foreign metal object detection method for the system
    Patent number: 9614395
    Abstract: A wireless charging system includes a wireless charging device and a power-consuming device installed in a charging area. The wireless charging device has a signal conversion module connected to a controller, a transmitter antenna and a power input terminal. The power-consuming device has a receiver coil connected to a rectifier and outputting generated power through a power output terminal. Before or when the wireless charging device charges the power-consuming device, the controller of the wireless charging device can detect a power consumption status, voltage and current information and phase difference information of the transmitter antenna to instantly determine if any foreign metal object enters the charging area, thereby preventing high temperature generated by the foreign metal object from causing equipment damage and danger and enhancing wireless charging safety.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 4, 2017
    Assignee: Automotive Research & Testing Center
    Inventors: Chao-Wen Chiang, Yu-Chuan Wang