Patents by Inventor Chuan Wang

Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170357082
    Abstract: On embodiment of the invention discloses an optical lens including five lens group and an aperture stop. Each lens group includes at least one lens with refractive power, and the aperture stop is fixed in a position between a second lens group and a third lens group. Further, a distance between a first lens group and a fifth lens group remains fixed during zooming or focusing, and respective distances of the second lens group and a fourth lens group relative to the fifth lens group vary during zooming or focusing.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 14, 2017
    Inventors: YUAN-HUNG SU, BING-JU CHIANG, KUO-CHUAN WANG
  • Publication number: 20170352144
    Abstract: A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 7, 2017
    Inventors: Shinn-Sheng YU, Anthony YEN, Wen-Chuan WANG, Sheng-Chi CHIN
  • Publication number: 20170347052
    Abstract: A video processing device capable of automatically determining an operation mode is provided. The video processing device includes a control signal processing circuit and a controller. The control signal processing circuit receives a control signal from a transmitter, and, according to at least one data access address indicated by the control signal, performs at least steps of determining whether the data access address satisfies a predetermined access address, and outputting a notification signal when the data access address satisfies the predetermined access address. The controller causes the video processing device to operate in a first mode according to the notification signal, and causes the video processing device to operate in a second mode when the notification signal is not received within a predetermined time interval.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Inventors: Chin-Lung Lin, Te-Chuan Wang, Chi-En Peng
  • Publication number: 20170344286
    Abstract: A solid state drive duplication apparatus having a plurality of duplication units, each of the duplication units including: a chain connection input port, a chain connection output port, a PCI-E interface, and a printed circuit board including an FPGA chip, wherein the duplication units are interconnected one another in a way that the chain connection output port of one unit of the duplication units is electrically connected with the chain connection input port of another unit of the duplication units; when in operation, a first unit of the duplication units outputs source data via the chain connection output port thereof, and each of other units of the duplication units uses the chain connection input port thereof to receive the source data and copy the source data into a solid state drive connected with the PCI-E interface thereof, and sends out the source data via the chain connection output port thereof.
    Type: Application
    Filed: October 6, 2016
    Publication date: November 30, 2017
    Inventor: Hong-Chuan WANG
  • Patent number: 9825196
    Abstract: The present invention relates to a microcrystalline silicon thin film solar cell and the manufacturing method thereof, using which not only the crystallinity of a microcrystalline silicon thin film that is to be formed by the manufacturing method can be controlled and adjusted at will and the defects in the microcrystalline silicon thin film can be fixed, but also the device characteristic degradation due to chamber contamination happening in the manufacturing process, such as plasma enhanced chemical vapor deposition (PECVD), can be eliminated effectively.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: November 21, 2017
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Min-Chuan Wang, Tian-You Liao, Chih-Pong Huang, Der-Jun Jan
  • Publication number: 20170330097
    Abstract: Systems and methods for assaying a test entity for a property, without measuring the property, are provided. Exemplary test entities include proteins, protein mixtures, and protein fragments. Measurements of first features in a respective subset of an N-dimensional space and of second features in a respective subset of an M-dimensional space, is obtained as training data for each reference in a plurality of reference entities. One or more of the second features is a metric for the target property. A subset of first features, or combinations thereof, is identified using feature selection. A model is trained on the subset of first features using the training data. Measurement values for the subset of first features for the test entity are applied to thereby obtaining a model value that is compared to model values obtained using measured values of the subset of first features from reference entities exhibiting the property.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Lee Chae, Josh Stephen Tetrick, Meng Xu, Matthew D. Schultz, Chuan Wang, Nicolas Tilmans, Michael Brzustowicz
  • Patent number: 9818652
    Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengwen Pei, Ping-Chuan Wang, Kai D. Feng
  • Patent number: 9817063
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ping-Chuan Wang, Andrew T. Kim, Ronald G. Filippi
  • Publication number: 20170322397
    Abstract: One embodiment of the invention discloses an optical imaging device including an optical lens. The optical lens has N number of lenses, and the N number of lenses are divided into a first lens group and a second lens group and have at least three aspheric lenses. The first lens group is disposed between an object side and an image side, and the first lens group has (N/2)?1 piece of lens. The first lens group includes, in order from the object side, a first lens, a second lens and a third lens, and the second lens is an aspheric lens. The second lens group is disposed between the first lens group and the image side, and an aperture stop is disposed between the first lens group and the second lens group.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 9, 2017
    Inventors: CHEN-CHENG LEE, HSIN-TE CHEN, KUO-CHUAN WANG
  • Publication number: 20170323937
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Application
    Filed: July 27, 2017
    Publication date: November 9, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9808016
    Abstract: The present invention provides a method of shortening pesticidal time of the baculovirus to pest, comprising: (1) preparing a pesticide composition; (2) diluting the pesticide composition 100-3000 times; and (3) spraying the diluted pesticide composition on third or older instars in fields; wherein the pesticide composition comprises: (a) a ryanodine receptor insecticide or a diamides insecticide and (b) baculovirus, wherein the concentration of the ryanodine receptor insecticide or the diamides insecticide is 0.01-75% and the concentration of the nucleopolyhedrovirus is 107-1012 PIB/ml. The pesticide composition of the present invention can effectively reduce the lethal time to the pest compared to the baculovirus alone, and also can increase the control effect of the pest compared to the same concentration of the insecticide, when applied in field.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 7, 2017
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Ju-Chun Hsu, Hsiang-Chuan Wang, Cheng-Jen Shih, Shu-Jen Tuan
  • Patent number: 9810994
    Abstract: The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Burn Jeng Lin, Shy-Jay Lin, Jaw-Jung Shin, Wen-Chuan Wang
  • Publication number: 20170316986
    Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 2, 2017
    Inventors: Chengwen Pei, Ping-Chuan Wang, Kai D. Feng
  • Publication number: 20170317166
    Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Chengwen Pei, Hanyi Ding, Ping-Chuan Wang, Kai D. Feng
  • Publication number: 20170307862
    Abstract: A zoom lens includes, in order from a magnified side to a minified side, a first lens group, an aperture stop, and a second lens group. The second lens group has at least one aspheric surface. The zoom lens satisfies the conditions: 0.1<Ic/TTLw<0.15 and TTLw/EFLw?10, where Ic denotes a radius of an image circle, TTLw denotes a total track length of the zoom lens in the wide configuration, and EFLw denotes an effective focal length of the zoom lens in the wide configuration.
    Type: Application
    Filed: April 25, 2016
    Publication date: October 26, 2017
    Inventors: Ying-Hsiu LIN, Kuo-Chuan WANG
  • Publication number: 20170309238
    Abstract: A display panel includes a substrate, and a pixel array and a gate driving circuit. The gate driving circuit provides gate driving signals to the pixel array, and includes shift registers, wherein each shift register includes a voltage providing unit, a first driving transistor, a voltage transmitting unit and a second driving transistor. The voltage providing unit receives a setting signal and a system high voltage to provide a first terminal voltage. The first driving transistor receives a first clock signal and the first terminal voltage to provide a first gate driving signal. The voltage transmitting unit receives the first gate driving signal to provide a second terminal voltage. The second driving transistor receives a second clock signal and the second terminal voltage to provide a second gate driving signal. Therefore, the influence caused by large difference of driving capabilities of the first and the second driving transistor is avoided.
    Type: Application
    Filed: May 9, 2016
    Publication date: October 26, 2017
    Inventors: Wei-Lien Sung, Han-Lung Liu, Wen-Chuan Wang, Shao-Lun Chang, Shih-Chieh Lin, Po-Tsun Liu, Guang-Ting Zheng, Shao-Huan Hung
  • Patent number: 9791852
    Abstract: A method for controlling at least one operational parameter of a plant (1) having a combustion unit (3) can include estimating a status of at least one operational variable of the plant to identify an estimated value for the operational variable. For each operational variable, the estimated value for the operational variable can be compared with a measured value of the operational variable to determine an uncertainty value based on a difference in value between the measured value and the estimated value for the operational variable. A control signal can be generated based on a reference signal, the measured value, and the deviation value for sending to at least one element of the plant (1) for controlling a process of the plant (1).
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 17, 2017
    Assignee: GENERAL ELECTRIC TECHNOLOGY GMBH
    Inventors: Xinsheng Lou, Chuan Wang, Carl H. Neuschaefer, Armand A. Levasseur
  • Patent number: 9792869
    Abstract: A display panel includes a substrate, and a pixel array and a gate driving circuit. The gate driving circuit provides gate driving signals to the pixel array, and includes shift registers, wherein each shift register includes a voltage providing unit, a first driving transistor, a voltage transmitting unit and a second driving transistor. The voltage providing unit receives a setting signal and a system high voltage to provide a first terminal voltage. The first driving transistor receives a first clock signal and the first terminal voltage to provide a first gate driving signal. The voltage transmitting unit receives the first gate driving signal to provide a second terminal voltage. The second driving transistor receives a second clock signal and the second terminal voltage to provide a second gate driving signal. Therefore, the influence caused by large difference of driving capabilities of the first and the second driving transistor is avoided.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 17, 2017
    Assignees: Chunghwa Picture Tubes, LTD., National Chiao Tung University
    Inventors: Wei-Lien Sung, Han-Lung Liu, Wen-Chuan Wang, Shao-Lun Chang, Shih-Chieh Lin, Po-Tsun Liu, Guang-Ting Zheng, Shao-Huan Hung
  • Publication number: 20170290695
    Abstract: A universally adjustable cervical collar is in the form of a U-shaped base with a front joined to a pair of rearwardly extending wings. Left and right planar chin supports are pivotally connected at their distal ends to the distal ends to of respective wings with a chin piece connected between the upper proximal ends of the chin supports. An adjustable latch is individually coupled between each wing and the lower proximal end of the associated chin supports.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 12, 2017
    Inventors: Thomas T. HAIDER, Chin-Chuan WANG
  • Publication number: 20170294499
    Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.
    Type: Application
    Filed: September 16, 2016
    Publication date: October 12, 2017
    Inventors: Chang Ming Lu, Chia-Yu Chen, Chih Pang Chang, Ching-Sang Chuang, Hung-Che Ting, Jung Yen Huang, Sheng Hui Shen, Shih Chang Chang, Tsung-Hsiang Shih, Yu-Wen Liu, Yu Hung Chen, Kai-Chieh Wu, Lun Tsai, Takahide Ishii, Chung-Wang Lee, Hsing-Chuan Wang, Chin Wei Hsu, Fu-Yu Teng