Patents by Inventor Chuan Wang

Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170293107
    Abstract: An optical lens including a first lens group and a second lens group is provided. The first lens group is arranged between a magnified side and a minified side. The first lens group includes a lens closest to the magnified side. A refractive power of the lens is negative, and at least one surface of the lens is an aspherical surface. The second lens group is arranged between the first lens group and the minified side. A distance between the first lens group and the second lens group is smaller than 0.7 millimeter. The optical lens is complied with conditions of 0.53<EFL/IH<0.7, FOV?150 degrees, and F?2.8, where EFL is an effective focal length, IH is an image height on an imaging plane at the minified side, FOV is a maximum field of view, and F is f-number.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 12, 2017
    Inventors: Kuo-Chuan Wang, Chen-Cheng Liao
  • Publication number: 20170293118
    Abstract: An imaging lens including a first lens group, a second lens group, and an aperture stop is provided. The first lens group is disposed between an object side and an image side. The second lens group is disposed between the first lens group and the image side. The aperture stop is disposed between the first lens group and the second lens group. The imaging lens includes at least three cemented lenses, each of the cemented lenses includes at least one lens having non-zero refractive power, and at least one lens of each of the cemented lenses has an Abbe number greater than 80.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 12, 2017
    Inventors: Wei-Hao Huang, Kuo-Chuan Wang, Bing-Ju Chiang
  • Publication number: 20170278927
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Application
    Filed: March 23, 2016
    Publication date: September 28, 2017
    Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
  • Patent number: 9772371
    Abstract: A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Charles J. Montrose, Ping-Chuan Wang
  • Patent number: 9774774
    Abstract: An image pickup apparatus includes a lens, an image sensor, an optical filter, and a driving device. The lens focuses light beams from at least one subject to form an optical image, and the image sensor receives the optical image and converts the optical image into at least one electric signal. The optical filter includes a first plate and a second plate, the first plate is disposed between the lens and the image sensor, and the second plate is disposed between the first plate and the image sensor. The driving device moves the second plate. The second plate has substantially the same index of refraction as the first plate, and a thickness of the second plate is continuously decreased or increased across the second plate.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: September 26, 2017
    Assignee: Young Optics Inc.
    Inventors: Chen-Cheng Lee, Hsin-Te Chen, Kuo-Chuan Wang, Yuan-Yu Lee
  • Patent number: 9768065
    Abstract: Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ping-Chuan Wang, Erdem Kaltalioglu, Ronald G. Filippi, Cathryn J. Christiansen
  • Patent number: 9768110
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9760834
    Abstract: Systems and methods for assaying a test entity for a property, without measuring the property, are provided. Exemplary test entities include proteins, protein mixtures, and protein fragments. Measurements of first features in a respective subset of an N-dimensional space and of second features in a respective subset of an M-dimensional space, is obtained as training data for each reference in a plurality of reference entities. One or more of the second features is a metric for the target property. A subset of first features, or combinations thereof, is identified using feature selection. A model is trained on the subset of first features using the training data. Measurement values for the subset of first features for the test entity are applied to thereby obtaining a model value that is compared to model values obtained using measured values of the subset of first features from reference entities exhibiting the property.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 12, 2017
    Assignee: Hampton Creek, Inc.
    Inventors: Lee Chae, Josh Stephen Tetrick, Meng Xu, Matthew D. Schultz, Chuan Wang, Nicolas Tilmans, Michael Brzustowicz
  • Patent number: 9761539
    Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Andrew T. Kim, Ping-Chuan Wang
  • Patent number: 9761411
    Abstract: A system and method for maskless direct write lithography are disclosed. The method includes receiving a plurality of pixels that represent an integrated circuit (IC) layout; identifying a first subset of the pixels that are suitable for a first compression method; and identifying a second subset of the pixels that are suitable for a second compression method. The method further includes compressing the first and second subset using the first and second compression method respectively, resulting in compressed data. The method further includes delivering the compressed data to a maskless direct writer for manufacturing a substrate. In embodiments, the first compression method uses a run-length encoding and the second compression method uses a dictionary-based encoding. Due to the hybrid compression method, the compressed data can be decompressed with a data rate expansion ratio sufficient for high-volume IC manufacturing.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: September 12, 2017
    Assignee: Taiwain Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin
  • Publication number: 20170254460
    Abstract: A connection structure for water input/output ports of a booster pump, that is used to connect to an outside pipeline through the water input/output ports of the booster pump, comprising: a fixing tube, formed integrally with an outer shell of the booster pump, and having a window hole on a side wall of the fixing tube; an insertion tube, with one end of the insertion tube connected to an outside pipeline, with one other end of the insertion tube inserted in the fixing tube, while a fastening slot is provided on a side wall of the insertion tube; and a fastening pin, inserted into the fixing tube to act in cooperation with the fastening slot, and when the insertion tube is inserted in the fixing tube, the fastening pin fixes and restricts the position of the insertion tube.
    Type: Application
    Filed: February 15, 2017
    Publication date: September 7, 2017
    Inventors: YUN-CHUAN WANG, JING-MING LI, JIAN-YONG YAN
  • Publication number: 20170254326
    Abstract: A pressure stabilization structure having a built-in integrally formed booster pump, comprising: a booster pump; a valve body, formed integrally with a shell of the booster pump, on the valve body is disposed a pressure release water input port and a pressure release water output port, a main valve core is disposed in an inner chamber of the valve body, that is movable to control the opening size of the pressure release water output port, and an auxiliary valve core is disposed in the inner chamber of the valve body, that is retractable to control the opening size of the pressure release water input port; a high pressure chamber, disposed on the booster pump, and is connected to the booster pump; and a low pressure chamber, disposed on the booster pump, and is connected to a the high pressure chamber through the valve body.
    Type: Application
    Filed: February 20, 2017
    Publication date: September 7, 2017
    Inventors: YUN-CHUAN WANG, JING-MING LI, JIAN-YONG YAN
  • Patent number: 9755591
    Abstract: An apparatus including: a plurality of amplifiers having a plurality of output ports, respectively, the plurality of amplifiers configured to amplify radio frequency (RF) signals received from at least one antenna; a plurality of demodulators configured to receive the amplified RF signals at a plurality of input ports, respectively, the plurality of demodulators configured to downconvert the received RF signals; and a plurality of switches configured to couple selected output ports of the plurality of amplifiers to selected input ports of the plurality of demodulators, wherein each switch of the plurality of switches is configured such that at least one of the plurality of output ports of the plurality of amplifiers is selectively coupled to any of multiple input ports of the plurality of input ports of the plurality of demodulators.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chuan Wang, Dongling Pan, Wing Fat Andy Lau, Jorge Andres Garcia, David Zixiang Yang
  • Patent number: 9755013
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Publication number: 20170242067
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Ping-Chuan Wang, Andrew T. Kim, Ronald G. Filippi
  • Patent number: 9741657
    Abstract: A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Shahab Siddiqui, Ping-Chuan Wang, Lijuan Zhang
  • Publication number: 20170227733
    Abstract: An optical lens including a first lens group and a second lens group is provided. The first lens group is arranged between a magnified side and a minified side. The first lens group includes three lenses. A surface of a second lens facing to the minified side is a convex aspherical surface. The second lens group includes three lenses. Each of the first lens group and the second lens group includes at least one aspherical lens.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Ying-Hsiu Lin, Kuo-Chuan Wang
  • Patent number: 9721854
    Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9717621
    Abstract: An adjustable cervical collar is in the form of a u-shaped base with a front joined to a pair of rearwardly extending wings. Left and right chin supports are pivotally connected at their distal ends to the distal ends to of respective wings with a chin piece connected between the upper proximal ends of the chin supports. An adjustable latch is individually coupled between each wing and the lower proximal end of the associated chin supports. Preferably the latch is in the form of 1) an arcuate slot in each wing arranged around the respective pivot axis with a track formed on opposite sides of the slot and 2) a retractable locking pin carried by each chin support and movable within the respective slot, the locking pins adapted to engage the ribs in the respective track to releasably lock the chin support to the respective wing.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 1, 2017
    Assignee: University Braces, LLC
    Inventors: Thomas T. Haider, Chih-Chuan Wang
  • Publication number: 20170201408
    Abstract: Wireless receivers are configured to support carrier aggregation. A device may include at least one low-noise amplifier (LNA). The device may also include a first input path configured to convey a first signal to a first input of the at least one LNA(s), and a second input path configured to convey a second signal to a second input of the LNA(s). Further, the device may include a transformer configured to inductively couple the first input path to the second input path.
    Type: Application
    Filed: June 7, 2016
    Publication date: July 13, 2017
    Inventors: Yunfei FENG, Chuan WANG, Dongling PAN, Chiewcharn NARATHONG