Abstract: The present invention discloses a planar CMOSFET structure used in the peripheral circuit of DRAM chip and in sense amplifiers of array core circuit of DRAM chip, the planar CMOSFET structure comprises a planar P type MOSFET with a first conductive region, a planar N type MOSFET with a second conductive region, and a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET; wherein the cross-shape localized isolation region includes a horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

Abstract: A transistor structure includes a substrate, a source region, a drain region, a trench, and a central pole. The substrate has a convex structure, wherein the convex structure has a conductive channel region. The source region contacts with a first end of the conductive channel region. The drain region contacts with a second end of the conductive channel region. The trench is formed in the convex structure and between the first end and the second end. The central pole is formed in the trench, wherein a material of the central pole is different from that of the conductive channel region.

Abstract: The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

Abstract: The present disclosure provides a data storage device. The data storage device includes a first area configured to store a first data; a second area configured to store a second data. The second data is associated with the first data, and the first data and/or the second data exclude an ECC.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: A ring input device, and more particularly to variable rotational resistance mechanisms within the ring input device that modulate the rotational friction of a rotating outer band to improve the user experience, is disclosed. Because finger rings are often small and routinely worn, electronic finger rings can be employed as unobtrusive communication devices that are readily available to communicate wirelessly with other devices capable of receiving those communications. Ring input devices according to examples of the disclosure can modulate the rotational friction of its rotating outer band in accordance with an item (e.g., user interface or parameter) being manipulated by the band.

Abstract: A semiconductor memory structure includes a plurality of DRAM cells, a bit line, and a sense amplifier. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. A capacitance of the bit line per DRAM cell is lower than 20×10?3 fF.

Abstract: An inductor and a power module are respectively provided. The inductor includes an insulating body and a conductive body. The insulating body has a top surface and a bottom surface. The conductive body includes two pin parts and a heat dissipation part. A portion of each of the pin parts is exposed outside the bottom surface. The portions of the two pin parts exposed outside the insulating body are configured to fix to a circuit board. The heat dissipation part is connected to the two pin parts, the heat dissipation part is exposed outside the top surface, and the heat dissipation part is configured to connect to an external heat dissipation member. When the inductor is fixed to the circuit board through the two pin parts exposed outside the bottom surface, the two pin parts and the bottom surface jointly define an accommodating space for accommodating a chip.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: The invention provides novel high-energy density and low-cost flow electrochemical devices incorporating solid-flow electrodes, and further provides methods of using such electrochemical devices. Included are anode and cathode current collector foils that can be made to move during discharge or recharge of the device. Solid-flow devices according to the invention provide improved charging capability due to direct replacement of the conventional electrode stack, higher volumetric and gravimetric energy density, and reduced battery cost due to reduced dimensions of the ion-permeable layer.

Abstract: A high-power seismic wave early warning method is provided to use an earliest-arriving seismic wave to estimate a maximum power value of a later-arriving high-power seismic wave for a target site. When the estimated maximum power value of the later-arriving high-power seismic wave is greater than a warning value, an earthquake early warning is transmitted to an earthquake early warning device that is located at the target site.

Abstract: A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.

Abstract: The present invention discloses a method to form a composite semiconductor wafer with a first dimension. The method comprises: attaching a set of thermal dissipation layers to a temporary carrier; bonding the temporary carrier with the set of thermal dissipation layers to a semiconductor substrate with the first dimension, such that the set of thermal dissipation layers are bonded to the semiconductor substrate; and removing the temporary carrier to form composite semiconductor wafer with the first dimension.

Abstract: Provided is an aqueous redox flow battery comprising a positive electrode, a negative electrode, a posolyte chamber containing a posolyte in a solvent, a negolyte chamber containing a polysulfide based negolyte and a soluble organic catalyst in a solvent, and a separator disposed between the posolyte chamber and the negolyte chamber, wherein the soluble organic catalyst has a potential lower than the polysulfide based negolyte.

Abstract: An electrical connector with a reinforced tongue has a package, an upper terminal set, a lower terminal set, and a median septum. The package is provided with a tongue. The upper terminal set is mounted in the package and includes multiple upper terminals. The lower terminal set is mounted in the package and includes multiple lower terminals. A median septum is mounted in the package and the tongue, is disposed between the upper terminal set and the lower terminal set, and has a protective wall formed onto two side edges and a front edge of the median septum and longitudinally extends, so as to form two tongue sides and a tongue tip of the tongue. A structural strength of the tongue can be greatly improved, so as to prevent the tongue from being damaged when the electrical connector is plugged or unplugged with improper angle or unsuitable force.

Abstract: An electric paper tray includes a base, a paper holding element pivotally mounted to at least one side of the base, a power unit arranged at the base, and a lifting module connected between the paper holding element and the power unit. The lifting module is movably mounted under the paper holding element. When the lifting module is driven by the power unit to move to a first position, with respect to the base, the lifting module drives the paper holding element to make the paper holding element rotate to a closed position, when the lifting module is driven by the power unit to move to a second position, with respect to the base, the lifting module drives the paper holding element to make the paper holding element rotate to an opened position.

Abstract: A standard cell includes plural of transistors including a first type transistor and a second type transistor, plural of contacts coupled to the transistors; at least one input line electrically coupled to the transistors; an output line electrically coupled to the transistors; a VDD contacting line electrically coupled to the transistors; a VSS contacting line electrically coupled to the transistors; wherein the first type transistor includes a first set of fin structures electrically coupled together, the second type transistor includes a second set of fin structures electrically coupled together, and a gap between the first type transistor and the second type transistor is not greater than 3×Fp minus A, wherein Fp is a pitch distance between two adjacent fin structures in the first type transistor and A is a minimum feature size of the standard cell.

Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

Abstract: Systems, methods, and devices are provided for providing intra-frame luminance scaling to avoid drawing excessive power while still providing exceptional brightness. An instantaneous average pixel luminance of an electronic display may be determined. The instantaneous average pixel luminance may correspond to an amount of light currently being emitted by the electronic display due to a previous image frame and a current image frame. Based at least in part on the instantaneous average pixel luminance, the luminance of a subset of pixels of image data of the current image frame may be adjusted, thereby allowing the electronic display to operate at a relatively high brightness level without exceeding a power limit.