Abstract: A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.

Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.

Abstract: In a method of manufacturing a semiconductor device, semiconductor layers, which are vertically arranged with a space between adjacent semiconductor layers, are provided over a substrate, an interfacial layer is formed around each of the semiconductor layers, a dielectric layer is formed on the interfacial layer around each of the semiconductor layers, a first conductive layer is formed on the dielectric layer, the first conductive layer is removed so that the dielectric layer is exposed, a second conductive layer is formed on the exposed dielectric layer so that the space between adjacent semiconductor layers is not fully filled by the second conductive layer, a third conductive layer is formed on the second conductive layer so that the space between adjacent semiconductor layers is filled by the third conductive layer, and the semiconductor layers are semiconductor wires or sheets.

Abstract: A light emitting device including a lighting unit and a conversion material is disclosed. The conversion material is configured to convert a part of the invisible light emitted from the lighting unit into a visible light, which indicates that the lighting unit is in operation. The spectral energy of visible light is less than 20% of the spectral energy measured within a wavelength range of 200 nm to 380 nm.

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Abstract: A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.

Abstract: A method of characterizing biological sequences includes: preparing a library of sequences; subjecting the sequences in the library to at least one screening experiment to obtain an experiment outcome of each of the sequences; creating a first dataset comprising identities of the sequences and the experiment outcomes of the sequences; and training a first neural network using the first dataset to extract first sequence features from the sequences in the first dataset. A second neural network may be additionally be trained using a second dataset based on an external database to generate a pre-trained model, which is used extract additional features from the first dataset.

Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Abstract: A heat dissipation system of a portable electronic device is provided. The heat dissipation system includes a body and at least one fan. A heat source of the portable electronic device is disposed in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet, at least one flow outlet, and at least one spacing portion. The flow outlet faces toward the heat source, and the spacing portion surrounds the flow inlet and abuts against the body, so as to isolate the flow inlet and the heat source in two spaces independent of each other in the body.

Abstract: A wideband antenna system includes a metal radiating portion, an aperture contact, a feed contact, an aperture tuner, an impedance tuner, a first switch, and a second switch. Two ends of the metal radiating portion respectively include a first contact and a second contact. The aperture contact is electrically connected to the metal radiating portion and is located between the first contact and the second contact. The feed contact is electrically connected to the metal radiating portion and is located between the first contact and the aperture contact. The aperture tuner is electrically connected to the aperture contact, and the impedance tuner is electrically connected to the feed contact. The first switch is electrically connected between the first contact and a zero-ohm resistor to selectively effect connection of the first contact to the zero-ohm resistor. The second switch is electrically connected between the first contact and the impedance.

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the etch stop layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

Abstract: A semiconductor structure and its manufacturing method are provided. A semiconductor structure includes a substrate and several bit lines on the substrate. Each of the bit lines includes a first conductive layer on the substrate, a second conductive layer on the first conductive layer, and a hardmask layer on the second conductive layer. The semiconductor structure further includes several contacts disposed on the substrate and positioned between two adjacent bit lines, wherein the bottom surfaces of the contacts physically contact the substrate. The top surfaces of the contacts are not higher than the top surfaces of the hardmask layers. Each of the contacts includes a bottom contact part on the substrate and a top contact part on the bottom contact part, and a width of a top surface of the top contact part is greater than a width of a top surface of the bottom contact part.

Abstract: A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.