Abstract: A projector and a projection method are provided. The projector includes a control device, a projection optical engine, a distance sensing device, and an image capturing device. The projection optical engine projects a first projection image to a projection surface according to first image data. The distance sensing device senses multiple distance parameters of a projection area. The image capturing device captures the first projection image to obtain a first captured image. The control device performs a keystone correction operation and a leveling correction operation on the first image data. The projection optical engine projects a second projection image to the projection surface according to the corrected first image data. The control device obtains a second captured image including the second projection image through the image capturing device, and analyzes the second captured image to project current projection image size information in the second projection image.

Abstract: A method for switching audio-visual interfaces and a circuit system are provided. The circuit system is disposed in a sink device. A protocol layer circuit of each of audio-visual interfaces in the sink device includes a status and control data channel control module, which is used to respond to the signals sent by the video sources continuously when the sink device is connected with audio-visual sources via the audio-visual interfaces. The multiple video sources can accordingly send FRL (fixed rate link) signals to the sink device in response to responses made by the sink device. The protocol layer circuit includes an FRL audio-visual packet detection module that starts to detect a rate of an FRL and resolve audio-visual packets for obtaining audio-visual data for the audio-visual interface that the sink device switches to.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A multimedia system and a protocol converter are provided. The multimedia system includes a sink device, e.g., a television, various audiovisual devices connected to the sink device, and the protocol converter. The protocol converter is connected to the sink device, and processes the audio and video signals inputted from a specific audiovisual source and outputted to the sink device to be played. The audio signals can be processed and played by an audio playback device directly connected with the protocol converter. Furthermore, the protocol converter can process the audio signals being returned from the sink device of the multimedia system via an audio return channel or an enhanced audio return channel. Finally, the received audio signals are converted and outputted to one of various audio output interfaces supported by the protocol converter.

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base and forming, on the base, a bit line contact region provided with a first groove; forming a first bit line contact layer in the first groove, wherein the first bit line contact layer in the first groove defines a second groove; forming a diffusion layer in the second groove, wherein the diffusion layer in the second groove defines a third groove; forming, in the third groove, a second bit line contact layer provided with a gap; and processing the diffusion layer.

Abstract: In one embodiment, a system comprising a battery set comprising plural battery cells configured in a circuit; and a control system configured to switch current flow in the circuit from bi-directional flow to and from the battery set to mono-directional flow to or from the battery set based on an over-charging or over-discharging condition.

Abstract: An ultrasound image system is provided. The ultrasound image system includes an ultrasound probe and a processing circuit. The ultrasound probe includes a substrate, a first transducer array and a second transducer array. The first transducer array is fixed disposed on the substrate and configured to receive a first ultrasound signal The second transducer array is fixed disposed on the substrate and configured to receive a second ultrasound signal. Each of the first transducer array and the second transducer array includes a plurality of ultrasound transducer elements arranged along a first direction. The ultrasound transducer elements of the first transducer array are interleaved with the ultrasound transducer elements of the second transducer array. The processing circuit is coupled to the first transducer array and the second transducer array and is configured to generate an ultrasound image signal according to the first ultrasound signal and the second ultrasound signal.

Abstract: An optical fiber scanning probe includes a rotor and at least one optical fiber. The rotor includes a torque rope rotatable about its central axis. The optical fiber is disposed on the rotor and eccentric relative to the torque rope. A central axis of the optical fiber is substantially parallel to the central axis of the torque rope. When the torque rope rotates about its central axis, the rotor brings a free end of the optical fiber to scan along an arc path.

Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.

Abstract: The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range.

Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

Abstract: A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.