Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220342455
    Abstract: A portable electronic device including a first body, a second body, a pivot element, a heat source, a first flexible heat conductive element, and a flip cover is provided. The pivot element is connected to the second body, and the second body is pivotally connected to the first body through the pivot element. The heat source is disposed in the first body. The first flexible heat conductive element is thermally coupled to the heat source and extends toward the pivot element from the heat source. The first flexible heat conductive element passes through the pivot element and extends into the inside of the second body and is thus thermally coupled to the second body. The flip cover is pivotally connected to the first body and located on a moving path of the pivot element.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 27, 2022
    Applicant: Acer Incorporated
    Inventors: Chun-Chieh Wang, Wen-Neng Liao, Cheng-Wen Hsieh, Chuan-Hua Wang, Yi-Ta Huang
  • Publication number: 20220336653
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Patent number: 11475952
    Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng, Chun-Chieh Chang
  • Publication number: 20220325962
    Abstract: A multi-loop cycling heat dissipation module including a first tank, a first pipe, a second tank, and a second pipe is provided. The first pipe is connected to the first tank to form a first loop, a first working fluid fills the first loop to transfer heat via phase transformation, and a first high-temperature section and a first low-temperature section are formed on the first pipe. The second pipe is connected to the second tank to form a second loop, a second working fluid fills the second loop to transfer heat via phase transformation, and a second high-temperature section and a second low-temperature section are formed on the second pipe. The first high-temperature section is in thermal contact with the second low-temperature section, and the first low-temperature section is in thermal contact with the second high-temperature section.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 13, 2022
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Chun-Chieh Wang, Tsung-Ting Chen, Chi-Tai Ho, Kuan-Lin Chen, Jau-Han Ke
  • Patent number: 11465250
    Abstract: A tool change unit includes a base and two tool arms rotatably mounted on the base and respectively located on two sides of the base. Each arm body includes a position-returning element, a gripping element, and an actuation element. The position-returning element enables the tool arm to rotate for upward and downward moving between a first position and a second position. The gripping element functions to grip a main-axle tool or a magazine tool. The tool change unit is combinable with a power unit to form a tool change device. The power unit drives the tool change unit to do rotation or rotation and upward and downward movement.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: October 11, 2022
    Inventor: Chun-Chieh Chen
  • Patent number: 11466055
    Abstract: A Hepatitis E virus (HEV)-based virus like nanoparticle (HEVNP) made with a modified capsid protein containing at least a portion of open reading frame 2 (ORF2) protein conjugated with gold nanocluster is provided. Also provided are methods of targeted delivery of a nucleic acid using the HEVNP.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: October 11, 2022
    Assignee: The Regents of the University of California
    Inventors: R. Holland Cheng, Chun Chieh Chen, Mohammad Ali Baikoghli, Marie Stark
  • Patent number: 11454997
    Abstract: A dynamic voltage compensation circuit suitable for performing voltage compensation between an electronic device and a multimedia device, and includes a current detection unit, a calculation module and a voltage output unit. The current detection unit is configured to obtain the output current of the electronic device outputting the multimedia device from the bus power terminal. The calculation module is configured to receive the output current and an ideal reference voltage, execute a voltage compensation algorithm to calculate a predetermined output voltage based on the output current, the ideal reference voltage, and a compensation coefficient, and generate a control signal according to the predetermined output voltage. The voltage output unit is configured to receive a control signal, and is controlled by the control signal to generate a compensated output voltage and output it to a bus power terminal.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: September 27, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chun-Chieh Chan, Hsing-Yu Lin, Yi-Cheng Lin
  • Patent number: 11454243
    Abstract: A data processing method is proposed, including: sensing, via at least one sensing portion, target information of a target device; receiving and processing, via an electronic device, the target information of the sensing portion to form feature information; processing, via the electronic device, the feature information into a label matrix, and establishing, via an artificial intelligence training method, a target model based on the label matrix; and after the electronic device captures real-time information of the target device, predicting, via the target model, a life limit of the target device, wherein a content of the target information is corresponding to a content of the real-time information. Thus, a good target model is constituted and is advantageous in training artificial intelligence by processing the feature information into the label matrix.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 27, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Hsiang Hsu, Chun-Chieh Wang, Hung-Tsai Wu
  • Publication number: 20220302116
    Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Huai-Tei Yang
  • Patent number: 11452232
    Abstract: Provided is an electronic device. The electronic device includes a housing, a heat generating element, a plurality of fans, and a guide structure. The housing includes a first outlet. The heat generating element is disposed in the housing. The fans are disposed in the housing. Each fan includes a second outlet. The second outlets at least partially face the interior of the housing. The guide structure is disposed in the housing, and is at least partially located between the fans. The guide structure at least partially extends toward the first outlet.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 20, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Chieh Wong, Cheng-Yu Wang
  • FAN
    Publication number: 20220290684
    Abstract: A fan adapted for being disposed in an electronic device is provided. The fan includes a hub and a plurality of metal blades respectively extending from the hub. Each of the metal blades has a root portion connected to the hub and an end portion away from the hub, and a mass of the end portion is greater than a mass of the root portion, such that the metal blade is elongated while the fan is rotated.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 15, 2022
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Chun-Chieh Wang, Han-Liang Huang, Sheng-Yan Chen, Tsung-Ting Chen
  • Publication number: 20220278159
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh FANG, Ming-Chi WU, Ji-Heng JIANG, Chi-Yuan WEN, Chien-Nan TU, Yu-Lung YEH, Shih-Shiung CHEN, Kun-Yu LIN
  • Patent number: 11430692
    Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Lun Tsai, Huei-Wen Hsieh, Chun-Sheng Chen, Kai-Shiang Kuo, Jen-Wei Liu, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 11426181
    Abstract: A tool for a bone implant includes a sleeve and a transmission rod including a transmission member disposed on an end of a shaft. Another end of the shaft is located outside of the sleeve. The transmission member is received in the sleeve and includes a first compartment and a plurality of first teeth surrounding the first compartment. A drilling rod includes a second compartment and a plurality of second teeth surrounding the second compartment. A coupling portion is disposed between the second compartment and a bit. The coupling portion is coupled with the sleeve. The bit is located outside of the sleeve. Two magnets are disposed in the first and second compartments, respectively. Two same poles respectively of the two magnets face each other.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: August 30, 2022
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Tung-Lin Tsai, Chun-Chieh Tseng, Yue-Jun Wang, Chun-Ming Chen, Li-Wen Weng, Pei-Hua Wang
  • Patent number: 11426407
    Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 30, 2022
    Assignee: Vertex Pharmaceuticals Incorporated
    Inventors: Mark Thomas Miller, Corey Anderson, Vijayalaksmi Arumugam, Brian Richard Bear, Hayley Marie Binch, Jeremy J. Clemens, Thomas Cleveland, Erica Conroy, Timothy Richard Coon, Bryan A. Frieman, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Sara Sabina Hadida-Ruah, Haripada Khatuya, Pramod Virupax Joshi, Paul John Krenitsky, Chun-Chieh Lin, Gulin Erdogan Marelius, Vito Melillo, Jason McCartney, Georgia McGaughey Nicholls, Fabrice Jean Denis Pierre, Alina Silina, Andreas P. Termin, Johnny Uy, Jinglan Zhou
  • Patent number: 11422964
    Abstract: An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port. The first configuration channel detection module is coupled to the first interface port through a first configuration channel pair, and configured to, after being communicated through a USB specification, detect a first configuration channel signal of a first input signal group to determine a signal type of the first input signal group, and control the first UFP physical layer module to output the first input signal group with a first signal configuration according to the signal type of the first input signal group.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 23, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chun-Chieh Chan, Wei-Lun Huang, Chia-Lung Hung, Yung-Ming Lin
  • Publication number: 20220262620
    Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Ting-Kui Chang, Chun-Chieh Lin
  • Patent number: 11414553
    Abstract: A fouling-proof structure is applicable to synthetic leather or fabric and it includes an alcohol-resistant layer; and a water-based fouling-proof layer disposed on the alcohol-resistant layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 16, 2022
    Assignee: JANTEC CORP.
    Inventors: Ching-Hsiang Chang, Kuo-Hsing Yeh, Chun-Chieh Wang
  • Patent number: 11418756
    Abstract: The present invention discloses a signal enhancement relay apparatus is provided. A display data channel stretching circuit includes a direct and an indirect channels. A snooper circuit is disposed at the direct channel. The indirect channel includes a master and a slave paths having a master and a slave transmission circuits disposed thereon. The direct channel is selected under a default passive mode such that a snooper link bridging handler circuit is enabled to monitor a display data transmission on the direct path through the snooper circuit, to perform a channel link bridging process corresponding to a data enhancement transmission channel accordingly.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chieh Chan, Chia-Hao Chang, Tai-Jung Wu, Ming-An Wu
  • Patent number: 11417729
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li