Abstract: An HDMI transmission device includes a packetizer circuit and a processor. A control method of controlling the HDMI transmission device includes performing a fixed rate link training, upon passing the fixed data rate link training, the processor transmitting an initial gap packet generation command to a controller of the packetizer circuit to output a selection signal to the packetizer circuit, so as to output an initial gap packet, when video data is not ready, continuously outputting the initial gap packet, when the video data is ready and a format change of the video data is detected or a signal abnormality unrelated to hot-plugging is detected, the processor transmitting a subsequent gap packet generation command to the controller to determine whether a block boundary is reached, and the controller switching the selection signal upon reaching the block boundary for the packetizer circuit to output the subsequent gap packet.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

Abstract: A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.

Abstract: A projection device includes a casing, a projection lens, and a fan. The casing includes a main body, a first base, and a second base, wherein the main body has a first side, a second side opposite to the first side, a middle section located between the first side and the second side, air inlet holes at least distributed in the middle section, and air outlet holes at least distributed in the middle section. The first base is installed on the first side, and the second base is installed on the second side. A minimum outer dimension of the main body falls in the middle section, and the air inlet holes face away from the air outlet holes. The projection lens is installed on the main body and located at the same side as the air outlet holes. The fan is installed in the main body.

Abstract: A transfer device including at least one first transfer component and at least one second transfer component are provided. The first transfer component includes a first carrier pad contacting the transferred object, and the second transfer component includes a second carrier pad contacting the transferred object, and material of the first carder pad has stronger capability to capture electrons than that of the second carrier pad and material of the second carrier pad has stronger capability to lose electrons than that of the first carder pad.

Abstract: A vapor chamber having an adhering configuration and a manufacturing method thereof are provided. The manufacturing method includes: a dispensing step implemented by forming a ring-shaped adhesive onto an inner surface of a first metallic sheet; a filling step implemented by filling a working liquid in a space jointly defined by the inner surface of the first metallic sheet and the ring-shaped adhesive; a bonding step implemented by bonding the first metallic sheet and a second metallic sheet together in a vacuum chamber through the ring-shaped adhesive, so as to form a semi-finished product that defines an enclosed thermal flow space therein, in which the working liquid is arranged in the thermal flow space; and a solidifying step implemented by placing the semi-finished product in a solidifying environment so as to solidify the ring-shaped adhesive to form a sealing frame.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A portable electronic device including a first body, a second body, a heat source, a first heat pipe, a second heat pipe, and a heat conducting element is provided. The second body is pivotally connected to the first body. The heat source is disposed in the first body and thermally coupled to the heat source. The second heat pipe is disposed in the first body and thermally coupled to the first heat pipe. The heat conducting element is connected to and thermally coupled to the second body, and the heat conducting element slidably contacts the second heat pipe and is thermally coupled to the second heat pipe.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.

Abstract: In some embodiments of the present disclosure, a method for forming a semiconductor device is described. A semiconductor layer is formed and a dielectric layer is formed. A pressurized treatment is performed to transform the semiconductor layer into a low-doping semiconductor layer and transform the dielectric layer into a crystalline ferroelectric layer. A gate layer is formed. An insulating layer is formed over the gate layer, the crystalline ferroelectric layer and the low-doping semiconductor layer. Contact openings are formed in the insulating layer exposing portions of the low-doping semiconductor layer. Source and drain terminals are formed on the low-doping semiconductor layer.

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

Abstract: A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.