Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11030928
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 8, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang
  • Patent number: 11026581
    Abstract: An optical probe for detecting a biological tissue includes a surface imaging module and a tomography capturing module. The surface imaging module captures and creates a surface image of the biological tissue, and at least includes a light source emitting a first detecting light. The tomography capturing module captures a tomography image of the biological tissue and receives a second detecting light. The first detecting light passes via a first optical path from the light source to an imaging sensor through the biological tissue, a telecentric lens, a first optical mirror, and a lens assembly in sequence. The second detecting light passes via a second optical path from a first collimator to the first collimator through a scanner, the first optical mirror, the telecentric lens, the biological tissue, the telecentric lens, the first optical mirror, the scanner, and the first collimator in sequence.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 8, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chy-Lin Wang, Yuan-Chin Lee, Chun-Chieh Huang, Hung-Chih Chiang, Chih-Ming Cheng, Shuen-Chen Chen
  • Publication number: 20210167571
    Abstract: A power-measuring protection method includes the steps of: applying an optical diffuser to attenuate a first laser light beam to form a second laser light beam; applying a photo detector to detect the second laser light beam to obtain an optical detection signal; applying a signal conversion module to transform the optical detection signal into a measurement data eigenvalue; applying a processor to receive the measurement and setting data eigenvalues, and to further transmit these data eigenvalues to an encoder; applying the encoder to encode the measurement data eigenvalue and the setting data eigenvalue, and then to transmit a corresponding measured encoded data and a corresponding set encoded data, respectively, to a control module; and, applying the control module to evaluate the set and measured encoded data to determine whether or not the high-power laser source needs to be stopped. In addition, a laser processing system is also provided.
    Type: Application
    Filed: December 26, 2019
    Publication date: June 3, 2021
    Inventors: CHIH-CHUN CHEN, FU-SHUN HO, CHUN-CHIEH YANG, YU-CHENG SONG
  • Publication number: 20210163238
    Abstract: A transfer device including at least one first transfer component and at least one second transfer component are provided. The first transfer component includes a first carrier pad contacting the transferred object, and the second transfer component includes a second carrier pad contacting the transferred object, and material of the first carder pad has stronger capability to capture electrons than that of the second carrier pad and material of the second carrier pad has stronger capability to lose electrons than that of the first carder pad.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 3, 2021
    Inventors: Zhen WANG, Zhiming LIN, Chun Chieh HUANG, Yu JING, Wenze WU
  • Publication number: 20210165473
    Abstract: A portable electronic device including a body, a door, a carrier and at least one electronic module is provided. The door is movably mounted on the body. The carrier includes a first side and a second side opposite to each other, the first side is pivoted to the body, and the second side is movably pivoted to the door. The electronic module is disposed on the carrier. At least one opening is formed between the door and the body when the door moves away from the body, and the door drives the carrier to rotate relative to the body, such that the electronic module is tilted with respect to the body along with the movement of the door, and the electronic module is exposed to an external environment via the opening for heat dissipation.
    Type: Application
    Filed: July 6, 2020
    Publication date: June 3, 2021
    Applicant: Acer Incorporated
    Inventors: Yi-Ta Huang, Chun-Chieh Wang, Wu-Chen Lee, Cheng-Nan Ling, Cheng-Wen Hsieh
  • Patent number: 11024671
    Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo, Tsai-Hao Hung
  • Patent number: 11024602
    Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Publication number: 20210151442
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 11009916
    Abstract: A touch input device includes a frame unit, a circuit unit and a touch pad. The circuit unit includes a circuit board, a dome-shaped actuating member including an actuating portion and a resilient metal sheet connected between the actuating portion and the circuit board, and a noise reduction member having a main body connected to the resilient metal sheet, made of an elastic material and formed with a recess surrounding the actuating portion. A touch surface of the touch pad is touchable to push the circuit unit toward the block member, such that the actuating portion contacts the block member to deform the resilient metal sheet to electrically connect the actuating portion with the circuit board.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 18, 2021
    Assignee: SUNREXTECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Yi-Wen Tsai, Ching-Yao Huang, Ling-Cheng Tseng
  • Patent number: 11011433
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 11011567
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Patent number: 11009971
    Abstract: An input device includes a wheel supporting structure, a scroll wheel, a hook part, a linking part, and a switching mechanism. The scroll wheel is rotatably supported by the wheel supporting structure, is exposed from the input device, and has a rotary shaft with a plurality of toothed slots thereon. The hook part is disposed biased on the wheel supporting structure to selectively engage with the toothed slots. The linking part is pivotally connected to the wheel supporting structure. The switching mechanism includes an abutting part and a switching part. The abutting part abuts against the linking part. The switching part is coupled to the abutting part. Therein, the switching mechanism is operable to move the abutting part through the switching part to rotate the linking part to abut against and move the hook part to disengage from the toothed slots.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 18, 2021
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Ching-Chin Chang, Wen-Yu Tsai, Feng-Wei Su, Chun-Chieh Chen
  • Publication number: 20210143278
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
  • Publication number: 20210142963
    Abstract: A trigger device includes a circuit board, an arched sheet, and a noise-reducing unit that includes first and second electroconductive sheets respectively connected to first and second nodes of the circuit board. The arched sheet is mounted to the second electroconductive sheet and is pressible from a preset state to a bent state, with the arched sheet being deformed and proximate to the first electroconductive sheet, and further from the bent state to a contact state, with the second electroconductive sheet being compressed and with a central portion of the arched sheet being brought into contact with the first electroconductive sheet to thus electrically connect the first and second nodes.
    Type: Application
    Filed: March 30, 2020
    Publication date: May 13, 2021
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh CHEN, Ling-Cheng TSENG, Ching-Yao HUANG
  • Patent number: 11004965
    Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Chun-Chieh Lu, Ming-Yang Li, Tzu-Chiang Chen
  • Patent number: 11000815
    Abstract: An automatic mixing machine includes a vessel, a shell, a motor, a mixing unit, a detection and feedback unit, a computing control unit and a drive unit. The shell is connected with the vessel to form a closed space. The motor is arranged in the shell. The first end of the mixing unit is connected with the motor, and the second end of the mixing unit extends into the closed space. The detection and feedback unit is electrically connected with the motor and collects at least one electric parameter of the motor. The computing control unit is electrically connected with the detection and feedback unit and generates a control signal according to the electric parameters and the mixing parameters. The drive unit is electrically connected with the computing control unit and the motor respectively, and outputs a drive signal to drive the motor according to the control signal.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 11, 2021
    Assignee: JU WORKS LTD.
    Inventors: Chun-Chieh Lee, Yen-Wei Liu, Hsun-Chang Wang, Yu-Ming Chan
  • Patent number: 11004196
    Abstract: Methods are herein provided for decision support in diagnosis of a disease in a subject, and for extracting features from a multi-slice data set. Systems for computer-aided diagnosis are provided. The systems take as input a plurality of medical data and produces as output a diagnosis based upon this data. The inputs may consist of a combination of image data and clinical data. Diagnosis is performed through feature selection and the use of one or more classifier algorithms.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: May 11, 2021
    Assignee: Koninklijke Philips N.V.
    Inventors: Lilla Boroczky, Lalitha Agnihotri, Luyin Zhao, Michael Chun-chieh Lee, Charles Andrew Powell, Alain C. Borczuk, Steven Kawut
  • Publication number: 20210132641
    Abstract: A dynamic voltage compensation circuit suitable for performing voltage compensation between an electronic device and a multimedia device, and includes a current detection unit, a calculation module and a voltage output unit. The current detection unit is configured to obtain the output current of the electronic device outputting the multimedia device from the bus power terminal. The calculation module is configured to receive the output current and an ideal reference voltage, execute a voltage compensation algorithm to calculate a predetermined output voltage based on the output current, the ideal reference voltage, and a compensation coefficient, and generate a control signal according to the predetermined output voltage. The voltage output unit is configured to receive a control signal, and is controlled by the control signal to generate a compensated output voltage and output it to a bus power terminal.
    Type: Application
    Filed: July 3, 2020
    Publication date: May 6, 2021
    Inventors: Chun-Chieh CHAN, Hsing-Yu LIN, Yi-Cheng LIN
  • Publication number: 20210133136
    Abstract: An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port.
    Type: Application
    Filed: July 7, 2020
    Publication date: May 6, 2021
    Inventors: CHUN-CHIEH CHAN, WEI-LUN HUANG, CHIA-LUNG HUNG, YUNG-MING LIN
  • Publication number: 20210134992
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Application
    Filed: July 12, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li