Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

Abstract: A manufacturing method of a porous biomedical implant includes the steps of providing a supporter having a bearing surface, forming the porous biomedical implant on the bearing surface by additive manufacturing and removing the supporter after additive manufacturing. The porous biomedical implant includes a solid part and a porous part, the solid part is coupled to the bearing surface of the supporter and the porous part is coupled to the solid part. Particularly, the solid and porous parts are created in same layers by additive manufacturing.

Abstract: A method includes obtaining, in electronic format, an image (102) including a medical image display region (104) and an information display region (106). The at least one of the medical image display region or the information display region includes graphical indicia representing at least one of an annotation (110, 112, 114, 116) or alphanumeric information (118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140). The method further includes evaluating pixels of the image to identify pixels including the graphical indicia representing an annotation or alphanumeric information of interest in the image. The method further includes extracting the annotation or alphanumeric information of interest from the identified graphical indicia from the image. The method further includes inserting the extracted annotation or alphanumeric information of interest in an electronically formatted clinical report for the image.

Abstract: A fibrocartilage suturing device is provided to solve the problem where the conventional procedure of the surgery is inconvenient. The fibrocartilage suturing device includes a tube assembly, a tubular member, and an anchor. The tube assembly extends through the tube assembly and includes an insertion section. The movement member is coupled with the tube assembly and includes a thrust rod extending through the tubular member. The anchor is located at one end of the thrust rod and includes a body and at least two wings connected to the body is able to be folded and unfolded relative to the body. The body of the anchor is connected to an end of a thread. Another end of the thread is connected to the tubular member.

Abstract: An automatic mixing machine including a vessel, a shell, a motor, a mixing unit, a detection and feedback unit, a computing control unit and a drive unit. The vessel is used for accommodating the raw materials. The shell is connected with the vessel to form a closed space. The motor is arranged in the shell. The first end of the mixing unit is connected with the motor, and the second end extends into the closed space. The detection and feedback unit is electrically connected with the motor and collects at least one electric parameter of the motor. The computing control unit is electrically connected with the detection and feedback unit and generates a control signal according to the electric parameters and the mixing parameters. The drive unit is electrically connected with the computing control unit and the motor respectively, and outputs a drive signal to drive the motor according to the control signal.

Abstract: A serial general purpose input/output system includes a transmitter, a cable, a receiver and a verification unit. The transmitter includes an encoder to perform cyclic redundancy check coding on a data to generate a cyclic redundancy check code for verifying the accuracy of the data, and a first serial general purpose input/output connector coupled to the encoder to transmit the data and the cyclic redundancy check code. The receiver includes a second serial general purpose input/output connector coupled to the first serial general purpose input/output connector by the serial general purpose input/output cable to receive the data and the cyclic redundancy check code from the first serial general purpose input/output connector.

Abstract: A debounce circuit includes a sampling circuit to sample an input signal four times at two adjacent rising edges and two adjacent falling edges of a first clock signal to determine a voltage level of the first output signal, a voltage level of the second output signal, a voltage level of the third output signal and a voltage level of the fourth output signal, and a logic gate for performing an AND operation or an OR operation on the first output signal, the second output signal, the third output signal, and the fourth output signal to output a debounced signal. The first clock signal has at least one of the two adjacent rising edges between the two adjacent falling edges and at least one of the two adjacent falling edges between the two adjacent rising edges.

Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.

Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.

Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: The present disclosure provides a mask assembly and a method for manufacturing the same, and a display device. The mask assembly includes a frame, a first mask and a second mask, and the first mask and the second mask are superposed on the frame; the first mask includes an opening region, the second mask includes an evaporation region in which a first evaporation hole is provided for allowing an evaporation material to pass therethrough and a buffer region surrounding the evaporation region and configured to block off the evaporation material, and an orthographic projection of the boundary of the opening region onto the second mask is located within the buffer region.

Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract: The present disclosure provides a cancer-specific or tissue specific targeting theranostic capsule using hepatitis E viral nanoparticle (HEVNP) to enhance the accuracy of cancer diagnosis in endoscopic examinations, as well as treatment, for example hyperthermia treatment, after diagnosis. The present disclosure also provides a method of delivering a theranostic agent using the endoscopic apparatus, as well as a non-transitory computer readable medium storing a program that causes a computer to execute the method of the present invention.