Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic device
    Patent number: 10638898
    Abstract: An electronic device including a self-propelled machine body and a portable machine body is provided. The self-propelled machine includes a moving module and has a first air flow channel. The portable machine body is detachably installed on the self-propelled machine body, and the portable machine body includes a suction motor. When the portable machine body is installed on the self-propelled machine body, the suction motor communicates with the first air flow channel, and the self-propelled machine body and the portable machine body are collectively actuated as a sweeping robot.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: May 5, 2020
    Assignee: IBOT Robotic Co. Ltd.
    Inventors: Tai-Yu Chiu, Chun-Chieh Huang
  • Health monitoring and safety protection for lithium ion battery modules and applications
    Patent number: 10641835
    Abstract: One embodiment of safety apparatus for a lithium ion battery module comprises a health monitoring component configured to detect degradation of a battery cell within the lithium ion battery module and transmit an output signal; and a safety protection component configured to receive the output signal and at least disable operation of the lithium ion battery module.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: May 5, 2020
    Assignee: ASCENDING ENERGY INC.
    Inventors: Andrew Pei-Chang Lee, Chun-Chieh Chang
  • METHODS OF MANUFACTURING REDISTRIBUTION CIRCUIT STRUCTURES
    Publication number: 20200135543
    Abstract: Methods of manufacturing redistribution circuit structures are disclosed and one of the methods includes the following steps. A seed layer is formed over a die and an encapsulant encapsulating the die. A photoresist material is formed over the seed layer. The photoresist material is exposed through a phase shift mask to an I-line wavelength within an I-line stepper using a numerical aperture equal to or less than 0.18. The photoresist material is developed to form a photoresist layer including photoresist patterns and openings therebetween. A conductive material is formed in the openings. The photoresist patterns are removed to form conductive patterns. By using the conductive patterns as a mask, the seed layer is partially removed, to form seed layer patterns under the conductive patterns, wherein redistribution conductive patterns include the seed layer patterns and the conductive patterns respectively.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Hung-Jui Kuo, Jaw-Jung Shin, Ming-Tan Lee
  • FORMATION AND IN-SITU ETCHING PROCESSES FOR METAL LAYERS
    Publication number: 20200135471
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • SOLAR CELL
    Publication number: 20200135947
    Abstract: A solar cell includes an N-type silicon substrate, a P-type doped region, an anti-reflective layer, an n+ back surface field (BSF), aluminum electrodes, aluminum doped regions, and a backside electrode. The N-type silicon substrate has a first surface and a second surface opposite to the first surface. The P-type doped region is formed in the first surface of the N-type silicon substrate. The anti-reflective layer is formed on the P-type doped region. The aluminum electrodes are formed on the P-type doped region, and the aluminum doped regions are formed in the P-type doped region under the aluminum electrodes, wherein the aluminum doped regions are in direct contact with the aluminum electrodes. The n+ BSF is formed in the second surface of the N-type silicon substrate, and the backside electrode is formed on the second surface of the N-type silicon substrate.
    Type: Application
    Filed: January 9, 2019
    Publication date: April 30, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Ming Yeh, Chorng-Jye Huang, Chun-Chieh Lo
  • METHOD AND SYSTEM FOR SCANNING WAFER
    Publication number: 20200134810
    Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.
    Type: Application
    Filed: February 26, 2019
    Publication date: April 30, 2020
    Inventors: PEI-HSUAN LEE, CHIEN-HSIANG HUANG, KUANG-SHING CHEN, KUAN-HSIN CHEN, CHUN-CHIEH CHIN
  • Formation method of semiconductor device with source/drain structures
    Patent number: 10636909
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Method for forming semiconductor device structure
    Patent number: 10636673
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The method includes performing a first planarization process over the second layer until the stop layer is exposed. The method includes performing an etching process to remove the second layer, the stop layer, and an upper portion of the first layer. The method includes performing a second planarization process over the first layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
  • Interconnect Structure for Stacked Device and Method
    Publication number: 20200127027
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Silicon Intermixing Layer for Blocking Diffusion
    Publication number: 20200126797
    Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.
    Type: Application
    Filed: March 1, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Chieh Wang, Kuo-Jung Huang, Yueh-Ching Pai, Huai-Tei Yang
  • High-K metal gate process and device
    Patent number: 10629700
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Wang Chun-Chieh, Yueh-Ching Pai, Chun-I Wu
  • Methods for forming transistor gates with hafnium oxide layers and lanthanum oxide layers
    Patent number: 10629496
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Shih-Chieh Chang
  • SYSTEMS AND METHODS FOR USING MACHINE LEARNING AND DNA SEQUENCING TO EXTRACT LATENT INFORMATION FOR DNA, RNA AND PROTEIN SEQUENCES
    Publication number: 20200118648
    Abstract: A method of characterizing biological sequences includes: preparing a library of sequences; subjecting the sequences in the library to at least one screening experiment to obtain an experiment outcome of each of the sequences; creating a first dataset comprising identities of the sequences and the experiment outcomes of the sequences; and training a first neural network using the first dataset to extract first sequence features from the sequences in the first dataset. A second neural network may be additionally be trained using a second dataset based on an external database to generate a pre-trained model, which is used extract additional features from the first dataset.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 16, 2020
    Inventor: Chun-Chieh CHANG
  • Biological sample processing device
    Patent number: 10620097
    Abstract: A biological sample processing device includes a base, a purification unit, a metering unit and a first tube. The purification unit is disposed on the base and is configured to purify a sample. The metering unit is disposed on the base and has an inlet, at least one metering trough and an overflow trough. The inlet is connected to the purification unit via the first tube, and the metering trough is connected between the inlet and the overflow trough. The sample from the purification unit is configured to enter the metering unit through the inlet to be moved toward the metering trough, and to be moved toward the overflow trough after the metering trough is filled with the sample.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 14, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-An Chen, Wen-Ching Lee, Tzu-Hui Wu, Pei-Shin Jiang, Ping-Jung Wu, Ruey-Shyan Hong, Hsiao-Jou Chang, Chun-Chieh Huang, Ting-Hsuan Chen, Chih-Lung Lin
  • FinFET Device and Methods of Forming Same
    Publication number: 20200105534
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More
  • APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR ELEMENTS, AND METHOD OF MAKING THE SAME
    Publication number: 20200105559
    Abstract: An apparatus for storing and transporting semiconductor elements includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pin holder integrally extending from the first rear side wall. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pivotal pin structure integrally coupled with and extending from the second rear side wall. The at least one pivotal pin structure comprises a shaft, and a head connected with the shaft. The at least one pin holder defines a cavity sized and shaped to accept the head of the at least one pivotal pin structure. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.
    Type: Application
    Filed: September 20, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hung Lin, Chun-Chieh Mo, Shih-Chi Kuo
  • High-K Metal Gate Process and Device
    Publication number: 20200105532
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chun-I Wu
  • SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    Publication number: 20200098865
    Abstract: A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh LU, Meng-Hsuan HSIAO, Tung-Ying LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    Publication number: 20200098866
    Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh LU, Meng-Hsuan HSIAO, Tung-Ying LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • Display screen with graphical user interface
    Patent number: D880513
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 7, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-An Wang, Ya-Fan Chou, Sih-Yu Chen, Chun-Chieh Hsu