Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • KEYBOARD
    Publication number: 20200402742
    Abstract: A keyboard includes a base plate, a hook structure, and a plastic engaging member. The base plate has a top surface. The hook structure is connected to the base plate and raised relative to the top surface. The plastic engaging member is located on the top surface and fixed to at least a part of the hook structure.
    Type: Application
    Filed: January 9, 2020
    Publication date: December 24, 2020
    Inventors: Chao-Chin HSIEH, Chun-Chieh CHAN
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20200403077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Semiconductor device and fabricating method thereof
    Patent number: 10872955
    Abstract: A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Meng-Hsuan Hsiao, Tung-Ying Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Communication device
    Patent number: 10873122
    Abstract: A communication device is provided. The communication device comprises a metal back cover electrically connected to a system ground plane; a first antenna unit for generating a first operating frequency band of the communication device; a second antenna unit for generating a second operating frequency band of the communication device. The first antenna unit includes a first signal source electrically connected to a first metal frame via a first matching circuit. The second antenna unit includes a second signal source electrically connected to a second metal frame via a second matching circuit. The first matching circuit and the second matching circuit are configured to adjust bandwidths and frequency ratios of the first operating frequency band and the second operating frequency band.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 22, 2020
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Po-Wei Lin, Chen-Min Yang, Tsung-Hsun Hsieh, Chun-Chieh Lin, Huan-Jyun Jiang, Zih-Guang Liao
  • Formation and in-situ etching processes for metal layers
    Patent number: 10872769
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Method of forming an interconnect structure having a carbon-containing barrier layer
    Patent number: 10867800
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • FinFET device and methods of forming same
    Patent number: 10867799
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More
  • Interconnect Structure Having a Carbon-Containing Barrier Layer
    Publication number: 20200388499
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Touch input device
    Patent number: 10861659
    Abstract: A touch input device includes a base board, a circuit module having a free end portion and a connecting end portion, a metallic connecting member and an annular, metallic frame. The connecting member includes a positioning portion fixedly mounted to the connecting end portion of the circuit module, and an elastic arm extending from the positioning portion away from the connecting end portion and toward a free end portion in such a way to define a coupling groove that indents away therefrom. The frame is spaced apart from the circuit module and includes a coupling portion that is embossed from a side of the frame proximate to the connecting member, and that has a coupling block coupled to the coupling groove of the elastic arm.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: December 8, 2020
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Yi-Wen Tsai, Ching-Yao Huang, Ling-Cheng Tseng
  • Interconnect structure for stacked device and method
    Patent number: 10861899
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • TOOL CHANGE UNIT AND TOOL CHANGE DEVICE INCLUDING SAME
    Publication number: 20200376618
    Abstract: A tool change unit includes a base and two tool arms rotatably mounted on the base and respectively located on two sides of the base. Each arm body includes a position-returning element, a gripping element, and an actuation element. The position-returning element enables the tool arm to rotate for upward and downward moving between a first position and a second position. The gripping element functions to grip a main-axle tool or a magazine tool. The tool change unit is combinable with a power unit to form a tool change device. The power unit drives the tool change unit to do rotation or rotation and upward and downward movement.
    Type: Application
    Filed: May 13, 2020
    Publication date: December 3, 2020
    Inventor: Chun-Chieh Chen
  • Capacitor having multiple graphene structures
    Patent number: 10854708
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Compact modeling for the negative tone development processes
    Patent number: 10852635
    Abstract: A photolithography model used in an optical proximity correction process modifies an image output intensity of a point disposed along a two dimensional plane and having coordinates (x,y) in accordance with a gradient of a convolution of a mask value at the point and a sampling pattern function selected at the point. The sampling pattern function includes, in part, a first subset of sampling patterns and a second subset of sampling patterns. The first subset of sampling patterns includes first and second nodes. The second subset of sampling patterns include first and second antinodes. The gradient of the convolution of the mask value and the first and second nodes of the first subset are scaled by a first coefficient. The gradient of the convolution of the mask value and the first and second antinodes of the second subset are scaled by a second coefficient.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 1, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Chun-Chieh Kuo, Jensheng Huang, Lawrence S. Melvin, III
  • METHOD OF MANUFACTURING PHASE SHIFT PHOTO MASKS
    Publication number: 20200371425
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • COMMUNICATION DEVICE
    Publication number: 20200373680
    Abstract: A communication device includes a display device, a first antenna element, a second antenna element, a third antenna element, and a fourth antenna element. The display device is surrounded by the first antenna element, the second antenna element, the third antenna element, and the fourth antenna element. Any adjacent two of the first antenna element, the second antenna element, the third antenna element, and the fourth antenna element have different polarization directions.
    Type: Application
    Filed: April 28, 2020
    Publication date: November 26, 2020
    Applicant: HTC Corporation
    Inventors: Cheng-Hung LIN, Szu-Po WANG, Chun-Chieh WANG, Yu-Yu CHEN, Shih-Hua WU, Dun-Yuan CHENG
  • CENTRIFUGAL HEAT DISSIPATION FAN
    Publication number: 20200370563
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet and at least one outlet. The impeller is disposed in the housing and rotates about an axis. The inlet is located in an axial direction of the axis and corresponds to the impeller. The outlet is located in a radial direction relative to the axis. The inlet is divided into a compression section and a release section in the rotation direction of the impeller, and the compression section has a uniform first radial dimension relative to the axis. The release section has an extended second radial dimension relative to the axis, and the second radial dimension is greater than the first radial dimension.
    Type: Application
    Filed: April 27, 2020
    Publication date: November 26, 2020
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Chun-Chieh Wang
  • Method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 10847736
    Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Yu-Ming Lin, Ken-Ichi Goto, Jean-Pierre Colinge, Zhiqiang Wu
  • Synthesis and characterization of lithium nickel manganese cobalt phosphorous oxide
    Patent number: 10847795
    Abstract: A novel chemical synthesis route for lithium ion battery applications focuses on the synthesis of a new active material using NMC (Lithium Nickel Manganese Cobalt Oxide) as the precursor for a phosphate material having a layered crystal structure. Partial phosphate generation in the layer structured material stabilizes the material while maintaining the large capacity nature of the layer structured material.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 24, 2020
    Assignee: CHANGS ASCENDING ENTERPRISE CO., LTD
    Inventors: Chun-Chieh Chang, Tsun Yu Chang
  • Negative Capacitance FET with Improved Reliability Performance
    Publication number: 20200365682
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • METHOD FOR FORMING INTEGRATED SEMICONDUCTOR DEVICE WITH 2D MATERIAL LAYER
    Publication number: 20200358873
    Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE