Abstract: A process for producing a low viscosity polyester polyol includes the steps of: (a) preparing a mixture which includes an aromatic diacid-based compound, an alkali metal ion-containing compound, and an aliphatic diol compound; and (b) subjecting the mixture to a reaction, wherein the alkali metal ion-containing compound has an alkali metal ion content of from 10 ppm to 12000 ppm based on a total weight of the mixture.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Abstract: A keyboard device includes a base plate and a plurality of keyswitches disposed on the base plate. At least one of the keyswitches includes a keycap, two linkages, and two magnetic attraction members. The linkages are connected between the base plate and the keycap and configured to guide the movements of the keycap toward and away from the base plate. The magnetic attraction members are rotatably connected to the linkages, respectively, and are configured to attract each other. When the magnetic attraction members abut against each other, the keycap is at a highest position relative to the base plate. When the keycap moves toward the base plate from the highest position, the magnetic attraction members are separated from each other.

Abstract: Disclosed are a 3D laser printer and its operation method. The 3D laser printer includes a body, a powder paving mechanism, a mobile preheating mechanism and a laser module. The body has a chamber, a carrying platform disposed in the chamber, and a feeding machine and a construction machine capable of descending and ascending with respect to the carrying platform. The powder paving mechanism is accommodated in the chamber and capable of moving reciprocately between the feeding machine and the construction machine. The mobile preheating mechanism is accommodated in the chamber and capable of moving reciprocately in at least one of the feeding machine and construction machine. The laser module is configured to be corresponsive to the construction machine. Therefore, non-heat resistant components such as a color printer head and a motor can be installed into the chamber directly to achieve the effects of diversified function and simple installation.

Abstract: A magnetoresistive random access memory (MRAM) structure and a method of forming the same are provided. The MRAM structure includes a conductive pillar over a substrate, a first MTJ spacer and a first conductive layer. The first MTJ spacer surrounds the conductive pillar. The first conductive layer surrounds the first MTJ spacer. The first magnetic tunnel junction (MTJ) spacer includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) layer. The first electrode is in contact with the conductive pillar and the substrate. The second electrode is positioned over the first electrode and in contact with the first conductive layer. The magnetic tunnel junction (MTJ) layer is positioned between the first electrode and the second electrode.

Abstract: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A portable electronic device having a heat source is provided with a suitable heat dissipation module. The heat dissipation module includes an evaporator, at least one pipe, a working fluid, and at least one check valve. The evaporator thermally contacts the heat source to transmit the heat generated by the heat source to the evaporator. The pipe is connected to the evaporator to form at least one loop, and the working fluid is filled in the loop. The working fluid absorbs and dissipates the heat in the loop to generate a phase change. The check valve is disposed at the loop and provides at least one recirculation channel in the same direction as the first direction and opposite to a second direction to block the working fluid from flowing in the second direction. The first and the second directions are opposite to each other.

Abstract: An image filing method including following steps is provided. At least one sheet is searched form from a plurality of scan image data by an office machine or a computer connected to the scanner. the plurality of scan image data is divided into M groups, and the at least one sheet form is set up in a first image data of each of M groups when there are M sheet forms searched from the plurality of scan image data, wherein M is an integral larger than 1. A keyword string is searched in each of the M sheet forms and an encoded string arranged after the keyword string is identified. M files corresponding to the M groups are created and named according to the encoded strings in each of the M sheet forms.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.

Abstract: The present disclosure provides a lightweight tile. The lightweight tile has a tile body and a lacquer layer overlaying on the tile body. The tile body is composed of a rigid foamed resin having a plurality of void cells. The density of the rigid foamed resin is 0.2 to 0.45 g/cm3. The lightweight tile provided in the present disclosure is less dense than the conventional ceramic tiles. In addition, the heat insulation and sound insulation of the lightweight tile are excellent.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.