Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10482820
    Abstract: A method of compensating luminance of an organic light-emitting diode (OLED) operated with a transistor in a pixel cell of a display panel includes measuring a first parameter of the transistor and a parameter of the OLED, and generating a lookup table accordingly; converting original display data to target display data according to the lookup table; outputting the target display data to the pixel cell; and compensating a second parameter of the transistor when the target display data is received by the pixel cell.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: November 19, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Hua-Gang Chang, Hsueh-Yen Yang, Shang-Yu Su, Feng-Ting Pai
  • Patent number: 10484560
    Abstract: An image capturing method and an image capturing device using the same are provided. The image capturing method includes the following steps. Firstly, the image capturing device receives a paper sheet having a plurality of regions. Then, the image capturing device provides a user interface. Then, in response to an operation of a user to the user interface, an arrangement regulation of the regions is set. Then, the image capturing device captures a plurality of region images of the regions of the paper sheet. Then, the image capturing device arranges the region images according to the arrangement regulation.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 19, 2019
    Assignee: AVISION INC.
    Inventor: Chun-Chieh Liao
  • Patent number: 10472464
    Abstract: A method for producing a polyester includes: a) preparing a first monomer represented by Formula (1) for example—bis(?-hydroxyethyl) terephthalate (BHET); and b) preparing a second monomer represented by Formula (2) represented by Formula (2)—2-(2-hydroxyethoxy)ethyl 2-hydroxyethyl terephthalate (BHEET). The prepared first and second monomer are then mixed to form a mixture, and then the mixture is subjected to a pre-polymerization reaction at a first temperature not higher than 230° C. to form a prepolymer while a glycol compound represented by Formula (3) wherein R independently represents hydrogen, a C1-C6 linear or branched alkyl group, or phenyl; is continuously removed by distillation. The method also includes subjecting the prepolymer to a polymerization reaction at a second temperature higher than the first temperature to obtain the polyester.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: November 12, 2019
    Assignee: FAR EASTERN NEW CENTURY CORPORATION
    Inventors: Chun-Chieh Chien, Chih-Chien Lin
  • Publication number: 20190341388
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: June 7, 2018
    Publication date: November 7, 2019
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 10465427
    Abstract: An electronic device and a hinge assembly thereof are provided. The hinge assembly has a first fixing block, a second fixing block, a first linking rod and a second linking rod. The first fixing block has a first end and a second end. The second fixing block has a third end and a fourth end. The first linking rod has a fifth end slidably and rotatably connected to the second end and a sixth end rotatably connected to the fourth end. The second linking rod has a seventh end slidably and rotatably connected to the fourth end and an eighth end rotatably connected to the second end. The sixth end has a groove portion and a first inclined surface, and the eighth end has a second inclined surface contacting the first inclined surface.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: November 5, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Jui Chen, Wei-Hao Lan, Che-Hsien Lin, Chen-Cheng Wang, Chun-Chieh Chen, Chia-Chi Lin, Han-Sheng Siao
  • Patent number: 10466429
    Abstract: An optical fiber module contains: a circuit board, a photoelectric assembly, a control assembly, a body, and a light transmission set. The body includes a first accommodation groove, a second accommodation groove accommodating the optoelectronic assembly, a first reflection portion facing the circuit board, a lens set accommodated in the second accommodation groove and aligning with the first reflection portion, a guide orifice, a converging lens extending from the guide orifice, and a second reflection portion adjacent to the converging lens, wherein the second reflection portion has a second reflecting face corresponding to the converging lens. The light transmission set includes multiple passing faces formed on a first surface thereof so as to face and correspond to the first reflection portion of the body, and the light transmission set includes multiple complete reflecting faces formed on a second surface thereof away from the multiple passing faces individually.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 5, 2019
    Assignee: ORANGETEK CORPORATION
    Inventors: Guan-Fu Lu, Chun-Yi Yeh, Chun-Chieh Chen, Chao-Hui Kuo
  • Patent number: 10468516
    Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 5, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang, Wen-Chia Liao, Ching-Chuan Shiue, Shih-Peng Chen
  • Patent number: 10469704
    Abstract: A controlled device, a control device, a control system using the same and a control method using the same are provided. The controlled device is configured for receiving a trigger event, and outputting a trigger signal in response to the trigger event. The control device is configured for receiving the trigger signal from the controlled device, and loading an application program corresponding to the trigger event in response to the trigger signal.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 5, 2019
    Assignee: AVISION INC.
    Inventor: Chun-Chieh Liao
  • Patent number: 10468530
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Publication number: 20190332321
    Abstract: A method for controlling a storage device is provided. The method may include: transmitting an initial command conforming to a first communications protocol and a data payload including a command parameter conforming to a second communications protocol to the storage device; transmitting a setting command conforming to the first communications protocol to the storage device; transmitting a confirmation command conforming to the first communications protocol to the storage device; and according to a data payload corresponding to the confirmation command, confirming whether the initial command, the setting command, and the confirmation command are successfully executed.
    Type: Application
    Filed: July 4, 2018
    Publication date: October 31, 2019
    Inventor: Chun-Chieh Chen
  • Publication number: 20190331135
    Abstract: A fan and a balance ring for the fan are provided. The fan includes a housing, a hub disposed in the housing, blades connected to the side surface of the hub, and a balance ring connected to the hub. The balance ring includes a ring chamber and a balance liquid filled in the ring chamber. The volume of the balance liquid is less than the volume of the ring chamber.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 31, 2019
    Inventors: Cheng-Wen HSIEH, Wen-Neng LIAO, Chun-Chieh WANG, Yu-Ming LIN
  • Publication number: 20190327403
    Abstract: A shooting device including a camera lens and a controller is provided. The camera lens is configured to shoot a picture. The controller, electronically coupled to the camera lens, divides the picture into a plurality of initial blocks each corresponding to an initial brightness value, selects at least one selection block from the initial blocks, and calculates an average brightness value according to the initial brightness value corresponding to the at least one selection block.
    Type: Application
    Filed: February 19, 2019
    Publication date: October 24, 2019
    Inventors: Yu-Lang WANG, Chun-Chieh LIAO
  • Patent number: 10453368
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 22, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang
  • Publication number: 20190319031
    Abstract: The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.
    Type: Application
    Filed: May 6, 2018
    Publication date: October 17, 2019
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Chun-Chieh Chiu, Chih-Chieh Tsai, Tzu-Chieh Chen, Chih-Chien Liu
  • Publication number: 20190318933
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20190319107
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Publication number: 20190317602
    Abstract: A touch input device includes a base board unit and an upper board unit. The base board unit includes opposite side ribs, opposite top and bottom surfaces, an intermediate portion disposed at the middle of one side rib, two flanking portions flanking the intermediate portion and two slots formed respectively through the flanking portions. The base board unit includes two resilient arms extending from the intermediate portion into the slots, respectively. The upper board unit is disposed on and above the base board unit and includes opposite sides correspond respectively in position to the side ribs, and two touch sensing modules respectively correspond in position to and spaced apart from the resilient arms.
    Type: Application
    Filed: August 27, 2018
    Publication date: October 17, 2019
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh CHEN, Ching-Yao HUANG, Ling-Cheng TSENG
  • Publication number: 20190317619
    Abstract: A touch input device includes a base board unit, an upper board unit, and a touched unit. The base board unit has an elongate opening having opposite opening ends respectively defined by two end walls. The upper board unit is disposed on and above the base board unit and includes a touched sensing module. The touched unit is mounted to the base board unit and includes two positioning seats, a touched portion, and two resilient arms. The positioning seats respectively abut against the end walls. The touched portion corresponding in position to the touched sensing module-is disposed. Each resilient arm interconnects the touched portion and a respective one of the positioning seats.
    Type: Application
    Filed: August 27, 2018
    Publication date: October 17, 2019
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh CHEN, Ching-Yao HUANG, Ling-Cheng TSENG
  • Publication number: 20190316840
    Abstract: A drying system and a drying method for a cleaning solution on a mask are disclosed. The drying system includes: a drying chamber having a first side wall and a second side wall arranged opposite to the first side wall; a plurality of first air knives on the first side wall and the second side wall for air-drying a cleaned mask; and a separation device for allowing a mask strip and a supporting and shielding strip to move away from each other at a spatial intersection region to increase a spacing between the mask strip and the supporting and shielding strip at the spatial intersection region, when the plurality of first air knives are air-drying the cleaned mask.
    Type: Application
    Filed: January 5, 2018
    Publication date: October 17, 2019
    Inventors: Zhiming Lin, Zhen Wang, Baojun Li, Zhi Yin, Chun-Chieh Huang
  • Patent number: 10446646
    Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu