Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446206
    Abstract: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Publication number: 20190310690
    Abstract: An electronic device includes a body, a driven component, a first magnetic component and a second magnetic component. The driven component is slidably disposed in the body. The first magnetic component is disposed at the driven component. The second magnetic component is located at one side of the driven component, and the first magnetic component and the second magnetic component are disposed corresponding to each other. The second magnetic component is configured to generate a magnetic attraction force or a magnetic repulsion force to the first magnetic component, so as to position the driven component based on the magnetic attraction force or the magnetic repulsion force between the first magnetic component and the second magnetic component.
    Type: Application
    Filed: March 31, 2019
    Publication date: October 10, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Jen-Ting Wei, Chen-Cheng Wang, Chun-Chieh Chen, Yuan-Xing Tsai
  • Publication number: 20190301661
    Abstract: The proposed vacuum jacketed tube may deliver the high/low temperature fluid with less temperature-transfer, especially may delivery high/low temperature fluid through a flexible structure. The vacuum jacketed tube includes a tubular structure surrounding a pipe wherein the fluid is delivered therethrough. Also, the space between the tubular structure and the pipe may be vacuumed. Therefore, the heat transferred into and/or away the fluid may be minimized, especially if the tubular structure and the pipe is separated by at least one thermal insulator or is separated mutually. Moreover, the vacuum jacketed tube may be mechanically connected to the source/destination of the delivered fluid, even other vacuum jacketed tube, through the bellows and/or the rotary joint. Besides, the pipe may be surrounded by a Teflon bellows and the tubular structure may be surrounded by a steel bellows, so as to further reduce the heat transferred into/away the fluid delivered inside the pipe.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Yu-Lin Chang, Chien-Cheng Kuo, Yu-Ho Ni, Chun-Chieh Lin
  • Publication number: 20190302580
    Abstract: A manufacturing method of a projection apparatus is provided. The manufacturing method of the projection apparatus includes: classifying a light valve by an optical jig; selecting an aperture stop with a size corresponding to classification of the light valve; and assembling the light valve and the aperture stop to form the projection apparatus.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Young Optics Inc.
    Inventors: Yu-Po Chen, Chun-Chieh Li, Wei-Szu Lin, Yi-Hsueh Chen
  • Publication number: 20190304792
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: June 3, 2019
    Publication date: October 3, 2019
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10429966
    Abstract: A touch input device includes a base board unit, a movable board unit, an actuating member and a noise reduction member. The base board unit has a distal end portion. The movable board unit overlaps and is connected to the base board unit, and has a free end portion movable toward or away from the distal end portion of the base board unit. The actuating unit includes a switch protruding from the free end portion and extending into the noise reduction member, and an actuating member protruding from the distal end portion. The noise reduction member is compressed by the distal end portion when the free end portion moves to the position adjacent to the distal end portion for the actuating member to actuate the switch.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 1, 2019
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Ching-Yao Huang, Ling-Cheng Tseng
  • Patent number: 10424622
    Abstract: A display device comprised of OLEDs and micro LEDs which allows for blue light degradation of the OLEDs includes a first substrate and a second substrate in a double-decked configuration. First light emitting elements are located and spaced on the first substrate and second light emitting elements are located and spaced on the second substrate, the light emitting elements on the lower deck being staggered so as not to be hidden by the light emitting elements on the upper deck. The upper deck has openings (or is transparent) therein to allow egress of light from the light emitting elements of the lower deck. The display device provides a solution for uneven display cause by degradation of pixels.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 24, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chang-Ting Lin, Wei-Chih Chang, Ying-Chieh Chen, Chung-Wen Lai, Chun-Chieh Huang, Wei-Li Wang, Po-Yi Lu, Jen-Jie Chen, I-Wei Wu
  • Publication number: 20190285700
    Abstract: One embodiment of safety apparatus for a lithium ion battery module comprises a health monitoring component configured to detect degradation of a battery cell within the lithium ion battery module and transmit an output signal; and a safety protection component configured to receive the output signal and at least disable operation of the lithium ion battery module.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: ANDREW PEI-CHANG LEE, CHUN-CHIEH CHANG
  • Publication number: 20190279022
    Abstract: An object recognition method and a device thereof are provided, the method includes: obtaining a plurality of key points of a test image and grayscale feature information of each of the key points, where the grayscale feature information is obtained according to a grayscale variation in the test image; obtaining hue feature information of each of the key points, where according to hue values of a plurality of adjacent pixels of the key point, the adjacent pixels are divided into a plurality of groups, and one of the groups is recorded as the hue feature information; and determining whether the test image is matched with a reference image according to the grayscale feature information and the hue feature information.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 12, 2019
    Applicant: Chunghwa Picture Tubes, LTD.
    Inventors: Chun-Chieh Chiu, Hsiang-Tan Lin, Pei-Lin Hsieh
  • Patent number: 10409013
    Abstract: An optical fiber module includes a main body and at least one optical conducting set. One surface of the main body is formed with a recess set and an accommodation groove, the main body is formed with a reflection slot and a lens slot, disposed with a lens set on a surface of the lens slot, and disposed with a third lens close to the accommodation groove; the optical conducting set is disposed in the accommodation groove and includes a base material and at least one optical conducting member, one surface of the base material is formed with an optical pervious plane close to the third lens which is substantially corresponding to the optical pervious plane, the optical conducting member are formed on two surfaces of the base materials, and can allow a light source with different wavelengths to pass and allow light sources with other wavelengths to be reflected.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 10, 2019
    Assignee: ORANGETEK CORPORATION
    Inventors: Guan-Fu Lu, Chun-Yi Yeh, Chun-Chieh Chen, Chao-Hui Kuo
  • Publication number: 20190269683
    Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.
    Type: Application
    Filed: January 25, 2019
    Publication date: September 5, 2019
    Applicant: Vertex Pharmaceuticals Incorporated
    Inventors: Mark Thomas Miller, Corey Anderson, Vijayalaksmi Arumugam, Brian Richard Bear, Haley Marie Binch, Jeremy J. Clemens, Thomas Cleveland, Erica Conroy, Timothy Richard Coon, Bryan A. Frieman, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Sara Sabina Hadida-Ruah, Haripada Khatuya, Pramod Virupax Joshi, Paul John Krenitsky, Chun-Chieh Lin, Gulin Erdogan Marelius, Vito Melillo, Jason McCartney, Georgia McGaughey Nicholls, Fabrice Jean Denis Pierre, Alina Silina, Andreas P. Termin, Johnny Uy, Jinglan Zhou
  • Patent number: 10395997
    Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 27, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Cheng Tsao, Cheng-Hung Wang, Chun-Chieh Lin, Hsiu-Hsiung Yang, Yu-Pin Tsai
  • Patent number: 10388207
    Abstract: An external compensation method for devices in a panel which comprises a plurality of sub-pixels, includes programming a first device in a first sub-pixel among the plurality of sub-pixels via a first line and sensing the first device via a second line during a first period; and programming a second device in a second sub-pixel among the plurality of sub-pixels via the second line and sensing the second device via the first line or a third line during a second period.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: August 20, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Hua-Gang Chang, Shang-I Liu, Chun-Chieh Lin
  • Publication number: 20190252241
    Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Ching-Chung SU, Jiech-Fun LU, Jian WU, Che-Hsiang HSUEH, Ming-Chi WU, Chi-Yuan WEN, Chun-Chieh FANG, Yu-Lung YEH
  • Publication number: 20190252390
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 15, 2019
    Inventors: Yi-Wei Chen, Pin-Hong Chen, Tsun-Min Cheng, Chun-Chieh Chiu
  • Publication number: 20190252489
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Publication number: 20190244804
    Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Ting-Kui Chang, Chun-Chieh Lin
  • Publication number: 20190244990
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20190243373
    Abstract: An automatic cleaning device including a first light sensor and a controller is provided. The first light sensor is disposed at a side position of a device body. The controller is coupled to the first light sensor. When the controller performs an automatic charging operation, the controller controls the device body of the automatic cleaning device to move forward and determines whether the first light sensor senses a light signal emitted by a light emitter of the charging dock. When the first light sensor senses the light signal, the controller records a first time parameter, and when the first light sensor no longer senses the light signal, the controller records a second time parameter. The controller determines whether to execute a first return mode or a second return mode according to a first time difference between the first time parameter and the second time parameter. In addition, an automatic charging method is also provided.
    Type: Application
    Filed: May 22, 2018
    Publication date: August 8, 2019
    Applicant: IBOT Robotic Co. Ltd.
    Inventors: Chia-Jui Kuo, Hung-Chou Chen, Chun-Chieh Huang
  • Publication number: 20190244999
    Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin