Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dose optimization based on outcome quality
    Patent number: 10289953
    Abstract: A system includes a modeler that generates a model which models a quality of findings in radiologist reports as a function of deposited dose of scans from which the radiologist reports are created and a dose optimizer that determines an optimal dose value for a planned scan based on the model and one or more optimization rules. A method includes generating a model which models a quality of findings in radiologist reports as a function of deposited dose of scans from which the radiologist reports are created and determining an optimal dose value tar a planned scan based on the model and one or more optimization rules.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 14, 2019
    Assignee: Koninklijke Philips N.V.
    Inventors: Michael Chun-chieh Lee, Eric Cohen-Solal
  • Synthesis and Characterization of Lithium Nickel Manganese Cobalt Phosphorous Oxide
    Publication number: 20190140274
    Abstract: Disclosed herein are certain embodiments of a novel chemical synthesis route for lithium ion battery applications. Accordingly, various embodiments are focused on the synthesis of a new active material using NMC (Lithium Nickel Manganese Cobalt Oxide) as the precursor for a phosphate material having a layered crystal structure. Partial phosphate generation in the layer structured material stabilizes the material while maintaining the large capacity nature of the layer structured material.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: CHUN-CHIEH CHANG, TSUN YU CHANG
  • APPARATUS AND METHOD FOR SENSING DISPLAY PANEL
    Publication number: 20190139471
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 9, 2019
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang
  • Semiconductor device and method of fabricating the same
    Patent number: 10283631
    Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 7, 2019
    Assignees: DELTA ELECTRONICS, INC., NATIONAL CENTRAL UNIVERSITY
    Inventors: Chun-Chieh Yang, Jen-Inn Chyi, Geng-Yen Lee
  • SEMICONDUCTOR DEVICE
    Publication number: 20190131214
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a first drain pad. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The first insulating layer is disposed on the source electrode, the drain electrode, and the gate electrode. The first source pad and the first drain pad are disposed on the first insulating layer and the active region. The first source pad includes a first source body and a first source branch. The first source branch is electrically connected to the first source body and disposed on the source electrode. The first drain pad includes a first drain body and a first drain branch. The first drain branch is electrically connected to the first drain body and disposed on the drain electrode.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Li-Fan LIN, Chun-Chieh YANG
  • SINGLE-BLADE-DOUBLE-EDGED STEEL WIRE ROPE SHEARS
    Publication number: 20190126368
    Abstract: A pair of single-blade-double-edged steel wire rope shears, includes: a first cutting member and a second cutting member pivotally connected to each other. The first cutting member includes a first grip and a first blade, the first blade includes a first lateral cutting edge and a first bottom cutting edge; the second cutting member includes a second grip and a second blade, the second blade includes a second lateral cutting edge and a second bottom cutting edge; when the first and second grips pivot toward each other, the first and second lateral cutting edges cut a to-be-cut object inserted therebeween, meanwhile, the first and second bottom cutting edges also cut the to-be-cut object, so as to form at least three cutting points on the to-be-cut object, and as a result, the pair of single-blade-double-edged steel wire rope shears can improve cutting efficiency.
    Type: Application
    Filed: December 25, 2018
    Publication date: May 2, 2019
    Inventors: SUNG-YU CHANG, CHUN-CHIEH LIAO
  • NEGATIVE CAPACITANCE FET WITH IMPROVED RELIABILITY PERFORMANCE
    Publication number: 20190131382
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190131425
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Chun-Chieh LU, Carlos H. DIAZ, Chih-Sheng CHANG, Cheng-Yi PENG, Ling-Yen YEH, Chien-Hsing LEE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190131420
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 2, 2019
    Inventors: Chun-Chieh LU, Carlos H. DIAZ, Chih-Sheng CHANG, Cheng-Yi PENG, Ling-Yen YEH
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190131426
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 2, 2019
    Inventors: Chun-Chieh LU, Cheng-Yi PENG, Chien-Hsing LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • Interconnect Structure for Stacked Device and Method
    Publication number: 20190131330
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 2, 2019
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Mechanisms for forming image-sensor device with expitaxial isolation feature
    Patent number: 10276622
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10276427
    Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ching-Chung Su, Jiech-Fun Lu, Jian Wu, Che-Hsiang Hsueh, Ming-Chi Wu, Chi-Yuan Wen, Chun-Chieh Fang, Yu-Lung Yeh
  • Semiconductor device and method for fabricating the same
    Patent number: 10276389
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Yi-Wei Chen, Pin-Hong Chen, Chih-Chien Liu, Tzu-Chieh Chen, Chun-Chieh Chiu, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang
  • Negative capacitance FET with improved reliability performance
    Patent number: 10276697
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
    Publication number: 20190123269
    Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 25, 2019
    Inventors: Chun-Chieh MO, Shih-Chi KUO
  • CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING CONDUCTIVE STRUCTURE
    Publication number: 20190122925
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
    Publication number: 20190123270
    Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 25, 2019
    Inventors: Chun-Chieh MO, Shih-Chi Kuo
  • Optical communication module
    Patent number: 10268001
    Abstract: An optical communication module contains: a lens element, a fixer, and at least one optical fiber. The lens element includes a groove, a body, a top face, a light input face, at least one collimator lens, and a reflective bevel face. The at least one collimator lens is located within an orthographic projection range of a vertical viewing angle of the reflective bevel face, and the body has a light output face. The fixer is mounted beside the body and includes an accommodation recess and at least one focus face, wherein the at least one focus face corresponds to an orthographic projection range of a horizontal viewing angle of the light output face. The at least one optical fiber is inserted into the accommodation recess, and a glue is filled into the accommodation recess so that the at least one optical fiber is adhered in the lens element.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Orangetek Corporation
    Inventors: Chun-Chieh Chen, Chao-Hui Kuo, Chun-Yi Yeh, Guan-Fu Lu
  • Hybrid bond pad structure
    Patent number: 10269770
    Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin