Patents by Inventor Chun-Hsiung Lin

Chun-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157995
    Abstract: A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Hong-Mao Lee, Huicheng Chang
  • Publication number: 20180350984
    Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Carlos H. DIAZ, Chun-Hsiung LIN, Huicheng CHANG, Syun-Ming JANG, Chien-Hsun WANG, Mao-Lin HUANG
  • Publication number: 20180350805
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Application
    Filed: July 26, 2018
    Publication date: December 6, 2018
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Patent number: 10109721
    Abstract: Various semiconductor devices, such as horizontal gate-all-around devices, and methods of fabricating such are disclosed herein. An exemplary semiconductor device includes a fin structure having a channel region disposed between a first source/drain region and a second source/drain region. The fin structure includes a first nanowire and a second nanowire disposed in the channel region, the first source/drain region, and the second source/drain region. The fin structure further includes an epitaxial layer that wraps the first nanowire and the second nanowire in the first source/drain region and the second source/drain region. A gate is disposed over the channel region of the fin structure, such that the gate wraps the first nanowire and the second nanowire in the channel region. In some implementations, the first nanowire, the second nanowire, and the epitaxial layer combine to have a vertical bar-like shape in the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Publication number: 20180219078
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: March 23, 2018
    Publication date: August 2, 2018
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20180174919
    Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure. The method also includes growing a first epitaxial region on the second portion of the first fin structure, removing the patterned first hard mask layer from the second portion of the second fin structure, patterning a second hard mask layer on the first epitaxial region, and growing a second epitaxial region on the second portion of the second fin structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: June 21, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Chieh SU, Chih-Hao WANG, Jui-Chen HUANG, Chun-Hsiung LIN
  • Patent number: 10002796
    Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure. The method also includes growing a first epitaxial region on the second portion of the first fin structure, removing the patterned first hard mask layer from the second portion of the second fin structure, patterning a second hard mask layer on the first epitaxial region, and growing a second epitaxial region on the second portion of the second fin structure.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Jui-Chien Huang, Chun-Hsiung Lin
  • Patent number: 9941374
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 9929248
    Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiang Fan, Chun-Hsiung Lin, Mao-Lin Huang
  • Patent number: 9911812
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Hsiung Lin, Carlos H. Diaz, Hui-Cheng Chang, Syun-Ming Jang, Mao-Lin Huang, Chien-Hsun Wang
  • Patent number: 9871101
    Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Chun-Hsiung Lin, Chien-Hsun Wang, Carlos H. Diaz
  • Patent number: 9865460
    Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Chun-Hsiung Lin, Mao-Lin Huang
  • Publication number: 20170358500
    Abstract: Various semiconductor devices, such as horizontal gate-all-around devices, and methods of fabricating such are disclosed herein. An exemplary semiconductor device includes a fin structure having a channel region disposed between a first source/drain region and a second source/drain region. The fin structure includes a first nanowire and a second nanowire disposed in the channel region, the first source/drain region, and the second source/drain region. The fin structure further includes an epitaxial layer that wraps the first nanowire and the second nanowire in the first source/drain region and the second source/drain region. A gate is disposed over the channel region of the fin structure, such that the gate wraps the first nanowire and the second nanowire in the channel region. In some implementations, the first nanowire, the second nanowire, and the epitaxial layer combine to have a vertical bar-like shape in the first source/drain region and the second source/drain region.
    Type: Application
    Filed: August 7, 2017
    Publication date: December 14, 2017
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Publication number: 20170356953
    Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 14, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han WANG, Chun-Hsiung LIN
  • Patent number: 9786757
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Chieh Su, Jui-Chien Huang, Chun-An Lin, Chien-Hsun Wang, Chun-Hsiung Lin
  • Patent number: 9773868
    Abstract: Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
  • Patent number: 9754840
    Abstract: A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 9735261
    Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
  • Publication number: 20170221890
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Application
    Filed: March 9, 2016
    Publication date: August 3, 2017
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Patent number: 9716096
    Abstract: A semiconductor structure includes a first fin structure, a gate structure, a first spacer, and a second space spacer. The gate structure traverses the first fin structure. The first fin structure has an exposed portion exposed out of the gate structure. The first spacer is positioned at and in contact with a side of the exposed portion of the first fin structure. The second space spacer is positioned at and in contact with another side of the exposed portion of the first fin structure. The first spacer has a top surface over than a top surface of the second spacer.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chun-Hsiung Lin, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz