Patents by Inventor Chun-Hsiung Lin

Chun-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170140996
    Abstract: A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 9620618
    Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
  • Publication number: 20170084717
    Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventors: Chun-Hsiang Fan, Chun-Hsiung Lin, Mao-Lin Huang
  • Publication number: 20170077253
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20170053827
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate structure over a substrate, forming a source/drain feature in the substrate adjacent the first gate structure, forming a dielectric layer over the first gate structure and the source/drain feature, removing a portion of the dielectric layer to form a first trench exposing the first gate structure and the source/drain feature, forming a first conductive feature in the first trench, removing a first portion of the first gate structure to form a second trench and forming a second conductive feature in the second trench.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 23, 2017
    Inventors: Chih-Hao Wang, Chun-Hsiung Lin, Chia-Hao Chang, Jia-Chuan You, Wei-Hao Wu, Yi-Hsiung Lin, Zhi-Chang Lin
  • Patent number: 9564363
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate structure over a substrate, forming a source/drain feature in the substrate adjacent the first gate structure, forming a dielectric layer over the first gate structure and the source/drain feature, removing a portion of the dielectric layer to form a first trench exposing the first gate structure and the source/drain feature, forming a first conductive feature in the first trench, removing a first portion of the first gate structure to form a second trench and forming a second conductive feature in the second trench.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Chun-Hsiung Lin, Chia-Hao Chang, Jia-Chuan You, Wei-Hao Wu, Yi-Hsiung Lin, Zhi-Chang Lin
  • Publication number: 20170025507
    Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 26, 2017
    Inventors: Chun-Hsiang Fan, Chun-Hsiung Lin, Mao-Lin Huang
  • Patent number: 9543419
    Abstract: An embodiment is a method including forming an epitaxial portion over a substrate, the epitaxial portion including a III-V material. A damaged material layer being on at least one surface of the epitaxial portion. The method further including oxidizing at least outer surfaces of the damaged material layer to form an oxide layer, selectively removing the oxide layer, and repeating the oxidizing and the selectively removing steps while at least a portion of the damaged material layer remains on the epitaxial portion.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiang Fan, Yung-Ta Li, Mao-Lin Huang, Chun-Hsiung Lin
  • Patent number: 9536738
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiung Lin, Chi-Wen Liu
  • Patent number: 9536962
    Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiang Fan, Chun-Hsiung Lin, Mao-Lin Huang
  • Patent number: 9508858
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 9508817
    Abstract: A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Sung Yen, Huan-Just Lin, Chun-Hsiung Lin, Chi-Cheng Hung
  • Publication number: 20160240378
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer.
    Type: Application
    Filed: March 6, 2015
    Publication date: August 18, 2016
    Inventors: Yu-Lien Huang, Chun-Hsiung Lin, Chi-Wen Liu
  • Publication number: 20160190272
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: HUAN-CHIEH SU, JUI-CHIEN HUANG, CHUN-AN LIN, CHIEN-HSUN WANG, CHUN-HSIUNG LIN
  • Publication number: 20160155817
    Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Inventors: Chien-Hsun WANG, Mao-Lin HUANG, Chun-Hsiung LIN
  • Publication number: 20160141361
    Abstract: Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.
    Type: Application
    Filed: January 22, 2016
    Publication date: May 19, 2016
    Inventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN, JEAN-PIERRE COLINGE
  • Publication number: 20160141423
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: October 1, 2015
    Publication date: May 19, 2016
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20160126143
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 5, 2016
    Inventors: HUAN-CHIEH SU, JUI-CHIEN HUANG, CHUN-AN LIN, CHIEN-HSUN WANG, CHUN-HSIUNG LIN
  • Patent number: 9312186
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Chieh Su, Jui-Chien Huang, Chun-An Lin, Chien-Hsun Wang, Chun-Hsiung Lin
  • Publication number: 20160079358
    Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Inventors: Gerben DOORNBOS, Chun-Hsiung LIN, Chien-Hsun WANG, Carlos H. DIAZ