NON-VOLATILE MEMORY
A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.
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This application claims the priority benefit of U.S. provisional applications Ser. No. 60/597,210, filed on Nov. 17, 2005 and 60/743,630, filed on Mar. 22, 2006, all disclosures are incorporated therewith.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory and a manufacturing method and an operation method thereof.
2. Description of Related Art
Electrically erasable programmable read-only memory (EEPROM) is a non-volatile memory wherein data can be written, read, or erased repeatedly, and the data stored in an EEPROM remains even when the power supply is turned off. Thus, EEPROM has become broadly applied to personal computers and other electronic apparatuses.
Presently, a non-volatile memory having a charge storage layer of silicon nitride is provided. Such silicon nitride charge storage layer usually has respectively a silicon oxide layer on the top and at the bottom, so as to form a memory cell of silicon-oxide-nitride-oxide-silicon (SONOS) structure. When voltages are supplied to the control gate and the source region/drain regions of the device to program the device, hot electrons are produced in the channel region and close to the drain region and are injected into the charge storage layer. The electrons injected into the charge storage layer are not distributed evenly in the entire charge storage layer, instead, the electrons stay in a particular area in the charge storage layer and present Gaussian distribution in the direction of the channel, thus, leakage current won't be produced easily.
However, when fabricating a SONOS memory, the gate of a SONOS memory cell in the memory cell region and the gate of a transistor in the logic circuit region are usually formed within the same step, and the oxide/nitride/oxide (ONO) layer of the SONOS memory cell and the gate oxide of the transistor in the logic circuit region are then patterned right after the gates are formed. However, since the thicknesses and structures of the oxide/nitride/oxide layer of the SONOS memory cell and the gate oxide of the transistor in the logic circuit region are very different, the thickness of the gate oxide becomes thinner and thinner along with the minimization of the device. Thus, it is very difficult to completely pattern the oxide/nitride/oxide layer of the SONOS memory cell and to prevent the substrate surface of the logic circuit region from being over-etched and producing recess. To resolve the foregoing problems, the SONOS memory cell in the memory cell region and the transistor in the logic circuit region are fabricated separately, and which complicates the fabricating process.
SUMMARY OF THE INVENTIONAccordingly, the present invention is directed to provide a non-volatile memory. The structure of the non-volatile memory is very simple, and the manufacturing process thereof is compatible with general logic circuit processes.
The present invention provides a non-volatile memory having a first memory cell formed on a first conductive type substrate. The first memory cell has a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at a first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at a second side of the gate, wherein the second side is opposite to the first side.
According to the non-volatile memory in an exemplary embodiment of the present invention, if the first conductive type is P-type, the second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second memory cell. The structure of the second memory cell is identical to that of the first memory cell, and the second memory cell and the first memory cell are formed in symmetric manner and share the second conductive type first lightly doped region.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second conductive type source region formed in the first conductive type substrate at the second side of the gate, wherein the second conductive type first lightly doped region is between the second conductive type source region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a first conductive type lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second conductive type second lightly doped region. The second conductive type second lightly doped region is formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second dielectric layer formed between the charge storage layer and the first conductive type substrate and between the charge storage layer and the gate.
According to the non-volatile memory in an exemplary embodiment of the present invention, the material of the charge storage layer includes silicon nitride.
The present invention provides a non-volatile memory having a plurality of memory cells, a plurality of source lines, a plurality of bit lines, and a plurality of word lines. The memory cells are formed on a first conductive type substrate and arranged as an array. Each of the memory cells has a gate, a second conductive type drain region, a charge storage layer, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at a first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type source region is formed in the first conductive type substrate at a second side of the gate, and the second side is opposite to the first side. The second conductive type first lightly doped region is formed between the second conductive type source region and the gate, wherein each of the memory cells shares the second conductive type source region or the second conductive type drain region with the adjacent memories cell in the same row. The source lines are arranged in parallel in the direction of columns and connect the second conductive type source regions in the same column. The bit lines are arranged in parallel in the direction of rows and connect the second conductive type drain regions in the same row. The word lines are arranged in parallel in the direction of columns and connect the gates of the memory cells in the same column.
According to the non-volatile memory in an exemplary embodiment of the present invention, if the first conductive type is P-type, the second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a first conductive type lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second conductive type second lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second dielectric layer formed between the charge storage layer and the first conductive type substrate and between the charge storage layer and the gate.
According to the non-volatile memory in an exemplary embodiment of the present invention, the material of the charge storage layer includes silicon nitride.
The present invention provides a non-volatile memory having a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. The memory cells are formed on a first conductive type substrate and arranged as an array. Each of the memory cells has a gate, a second conductive type drain region, a charge storage layer, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at a first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type source region is formed in the first conductive type substrate at a second side of the gate, and the second side is opposite to the first side. The second conductive type first lightly doped region is formed between the second conductive type source region and the gate, wherein the memory cells are connected in series in the direction of rows. The bit lines are arranged in parallel in the direction of columns and connect the second conductive type drain regions and the second conductive type source regions in the same column. The word lines are arranged in parallel in the direction of rows and connect the gates of the memory cells in the same row.
According to the non-volatile memory in an exemplary embodiment of the present invention, if the first conductive type is P-type, the second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a first conductive type lightly doped region: formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second conductive type second lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
According to an exemplary embodiment of the present invention, the non-volatile memory further includes a second dielectric layer formed between the charge storage layer and the first conductive type substrate and between the charge storage layer and the gate.
According to the non-volatile memory in an exemplary embodiment of the present invention, the material of the charge storage layer includes silicon nitride.
According to a non-volatile memory in the present invention, the charge storage layer of a memory cell is formed on the sidewall of the gate structure, which is different from the conventional technique that the oxide/nitride/oxide (ONO) layer of a silicon-oxide-nitride-oxide-silicon (SONOS) memory is formed below the gate. The structure in the present invention can greatly reduce the size of the device.
Moreover, the manufacturing method of non-volatile memory in the present invention can be integrated with a typical complementary metal-oxide semiconductor (CMOS) manufacturing process and no photolithography etching process of multiple masks is required, thus, the manufacturing time of a device can be shortened.
Furthermore, in a memory cell of the present invention, a lightly doped region of the same conductive type as that of the source region is formed at the source, and no lightly doped region is formed at the drain or the substrate at the drain is neutralized, or even a lightly doped region of the inverse conductive type as that of the drain region is formed at the drain. Thus, regardless right-reading or inverse reading, the turn-on current at reading the memory cell is smaller so that the device can have better performance.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIGS. 4A˜4E are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to an exemplary embodiment of the present invention.
FIGS. 5A˜5B are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to an exemplary embodiment of the present invention.
FIGS. 6A˜6C are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to an exemplary embodiment of the present invention.
FIGS. 7A˜7D are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to an exemplary embodiment of the present invention.
FIGS. 8A˜8C and
FIGS. 8D˜8E are diagrams illustrating the operation of a P-type non-volatile memory.
Referring to
The gate 104 is, for example, formed on the first conductive type substrate 100. The material of the gate 104 is, for example, doped polysilicon.
The gate dielectric layer 102 is, for example, formed between the gate 104 and the first conductive type substrate 100. The material of the gate dielectric layer 102 is, for example, silicon oxide.
The second conductive type source region 110 and the second conductive type drain region 112 is, for example, formed in the first conductive type substrate at two sides of the gate 104.
The charge storage layers 108a and 108b is, for example, formed on the sidewall of the gate 104, wherein the charge storage layer 108a is formed on the substrate between the second conductive type drain region 112 and the gate 104, and the charge storage layer 108b is formed on the substrate between the second conductive type source region 112 and the gate 104. In the present embodiment, only the charge storage layer 108a is used for storing charges, while the charge storage layer 108b is not for storing charge but can be considered as an insulating spacer. The material of the charge storage layers 108a and 108b is, for example, silicon nitride. However, the material of the charge storage layers 108a and 108b is not limited to silicon nitride but may also be other material which can trap charges, such as SiON, TaO, SrTiO3, or HfO2.
The second conductive type lightly doped region 114 is, for example, formed in the first conductive type substrate 100 between the gate 104 and the second conductive type source region 110, namely, below the charge storage layer 108b.
In the embodiment described above, if the first conductive type is P-type, then the second conductive type is N-type, and the memory cell is a N-channel memory cell; if the first conductive type is N-type, then the second conductive type is P-type, and the memory cell is a P-channel memory cell.
In a memory cell of the present invention, since there is no second conductive type lightly doped region formed at the second conductive type drain region 112, the charge storage layer 108a can be used for storing charges. The second conductive type lightly doped region 114 is formed at the second conductive type source region 110, and then the charge storage layer 108b cannot be used for storing charges. The structure of the memory cell in the present invention is very simple and the manufacturing method can be integrated with a typical complimentary metal-oxide semiconductor (CMOS) manufacturing process.
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In the memory cell 101b shown in
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In the memory cell 101c shown in
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In the memory cell 101d as shown in
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Since two memory cells share one second conductive type source region 110, the device integration can be increased. A memory unit 101e composed of two memory cells 101a is illustrated in
FIG. IF is a cross-sectional diagram of a non-volatile memory cell according to yet another exemplary embodiment of the present invention. In
As shown in
In the non-volatile memory of the present invention, the charge storage layer is formed on the sidewall of the gate structure, and which is different from that the oxide/nitride/oxide (ONO) layer of a conventional SONOS memory is formed below the gate. The structure in the present invention can greatly reduce device size. The manufacturing process of the non-volatile memory in the present invention is simple and no photolithography process of multiple masks is required, furthermore, the process can be integrated with a typical CMOS process, thus, the manufacturing time of device can be shortened. Besides, the second conductive type drain regions 112 in the non-volatile memories in FIGS. 1A˜1F do not have to be self aligned to the gate.
As shown in
The memory cells Q11˜Q46 are arranged as an array. The memory cells Q11˜Q16 are, for example, formed in symmetric manner in direction X (the direction of rows). Two adjacent memory cells among memory cells Q11˜Ql6 share one source region S or one drain region D. For example, the memory cells Q11 land Q12 share the drain region D1, the memory cells Q13 and Q14 share the drain region D2, and the memory cells Q15 and Q16 share the drain region D3. The memory cells Q12 and Q13 share the source region S2, and the memory cells Q14 and Q15 share the source region S3.
The source lines SL1˜SL4 are arranged in parallel in direction Y (the direction of columns) and connect the source regions of the memory cells in the same column. For example, the source line SL1 connects the source regions of the memory cells Q11˜Q41, the source line SL2 connects the source regions of the memory cells Q12˜Q41 and the memory cells Q13˜Q43, . . . , the source line SL4 connects the source regions of the memory cells Q16˜Q46.
The bit lines BL1˜BL4 are arranged in parallel in direction X (the direction of rows) and connect the drain regions of the memory cells in the same row. For example, the bit line BL1 connects the drain regions of the memory cells Q11˜Q16, the bit line BL2 connects the drain regions of the memory cells Q21˜Q26, . . . , the bit lines BL4 connects the drain regions of the memory cells Q41˜Q46.
The word lines WL1˜WL6 are arranged in parallel in the direction of columns and connect the gates of the memory cells in the same column. For example, the word line WL1 connects the gates of the memory cells Q11˜Q41, the word line WL2 connects the gates of the memory cells Q12˜Q42, . . . , the word line WL6 connects the gate of the memory cells Q16˜Q46.
As shown in
The memory cells Q11˜Q46 are arranged as an array. In direction X (the direction of rows), the memory cells Q11˜Q16 are, for example, connected in series, the memory cells Q21˜Q26 are, for example, connected in series, . . . , the memory cells Q41˜Q46 are, for example, connected in series. Here series connection refers to that the source region of a memory cell is connected to the drain region of the previous adjacent memory cell, and the drain region of the memory cell is connected to the source region of the next memory cell. That is, in the direction of rows, two adjacent memory cells share one doped region S/D, and the S/D is used as the source region of a memory cell and the drain region of the other memory cell.
The bit lines BL1˜BL7 are arranged in parallel in direction Y (the direction of columns) and connect the doped regions S/D in the same column. For example, the bit line BL1 connects the doped regions S/D at one side of the memory cells Q11˜Q41, the bit line BL2 connects the doped regions S/D between the memory cells Q12˜Q42 and the memory cells Q13˜Q42, . . . , the bit line BL6 connects the doped regions S/D between the memory cells Q15˜Q45 and the memory cells Q16˜Q46, the bit line BL7 connects the doped regions S/D at the other side of the memory cells Q16˜Q46.
The word lines WL1˜WL6 are arranged in parallel in the direction of rows and connect the gates of the memory cells in the same row. For example, the word line WL1 connects the gates of the memory cells Q11˜Q16, the word line WL2 connects the gates of the memory cells Q21˜Q26, . . . , the word line WL4 connects the gates of the memory cells Q41˜Q46.
In a memory cell array of the present invention, the charge storage layers of the memory cells Q11˜Q46 are formed on the sidewalls of the gates, and such structure can greatly reduce device size. The manufacturing process is very simple and no photolithography process of multiple masks is required, further more, the manufacturing process can be integrated with a typical CMOS process, so that the manufacturing time of the device can be shortened.
Next, the manufacturing method of a non-volatile memory in the present invention will be described. FIGS. 4A˜4E are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to an exemplary embodiment of the present invention.
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FIGS. 5A˜5B are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to another exemplary embodiment of the present invention. The components in FIGS. 5A˜5B same as those in FIGS. 4A˜4E have the same reference numerals and the descriptions thereof are skipped herein.
Referring to
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FIGS. 6A˜6C are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to yet another exemplary embodiment of the present invention. The components in FIGS. 6A˜6C same as those in FIGS. 4A˜4E have the same reference numerals and the descriptions thereof are skipped herein.
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FIGS. 7A˜7D are cross-sectional diagrams illustrating the manufacturing flow of a non-volatile memory according to an exemplary embodiment of the present invention. The components in FIGS. 7A˜7D same as those in FIGS. 4A˜4E have the same reference numerals and the descriptions thereof are skipped herein.
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According to the manufacturing method of non-volatile memory in the present invention, the charge storage layer is formed on the sidewall of the gate structure, and which is very different from the conventional technique that the ONO layer of a SONOS memory is formed below the gate. Thus, the manufacturing method of non-volatile memory in the present invention can be integrated with a typical CMOS process and can shorten the time required for manufacturing the device.
Next, the operation method in the present invention will be described. First, an N-channel memory cell will be described. FIGS. 8A˜8C and
The voltage levels described below comply with foregoing parameter.
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Next, the reading method of the present invention will be described.
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According to the operation method of a non-volatile memory in the present invention, charges stored in the memory cell may also be erased by high power radiation (for example, ultraviolet radiation) or by FN tunneling effect.
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According to the operation method of a non-volatile memory in the present invention, electrons or holes are injected into the charge storage layer by one of channel hot electron injection, band-to-band tunneling induced hot hole injection, drain breakdown induced hot hole injection, and channel hot carrier induced secondary carrier injection, so as to program/erase the memory cell. Right reading or inverse reading can be performed to the non-volatile memory in the present invention. Besides, charges stored in the memory cell may also be erased by using high power radiation (for example, ultraviolet radiation) or FN tunneling effect.
Besides, in the memory cell of the present invention, a lightly doped region of the same conductive type as that of the source region at the source, no lightly doped region is formed at the drain or the substrate at the drain is neutralized, or even a lightly doped region of the inverse conductive type of that of the drain region is formed at the drain, so that at reading the memory cell, regardless right reading or inverse reading, the memory cell in the present invention has smaller turn-on current and better device performance compared to conventional memory cell wherein lightly doped regions of the same conductive type as that of the source region are formed at both the source and the drain.
Next, the operations of a non-volatile memory array in the present invention will be described, which includes programming, erasing, and data reading. An exemplary embodiment of the operation method of a non-volatile memory will be described below, however, the operation method is not limited thereto. The memory unit Q13 illustrated in
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In foregoing description, the operations are performed to only one memory cell in the memory cell array, however, the programming, erasing, or reading operation may also be performed to memory cells in unit of bite, section, or block by controlling the word lines, source lines, and bit lines in a non-volatile memory array of the present invention.
The operation patterns of another non-volatile memory array in the present invention will be described next. The operations include programming, erasing, and data reading. The memory cell Q13 illustrated in
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In foregoing description, the operations are performed to only one memory cell in the memory cell array, however, the programming, erasing, or reading operation may also be performed to memory cells in unit of bite, section, or block by controlling the word lines, source lines, and bit lines in a non-volatile memory array of the present invention.
In overview, in a non-volatile memory of the present invention, the charge storage layer of a memory cell is formed on the sidewall of the gate structure, and which is different from that in a conventional SONOS, the ONO layer is formed below the gate. The structure in the present invention can greatly reduce the size of the device.
Moreover, the manufacturing method of a non-volatile memory in the present invention can be integrated with a typical CMOS process and no photolithography etching process with multiple masks is required, thus, the manufacturing time of the device can be shortened.
Furthermore, according to a memory cell in the present invention, a lightly doped region of the same conductive type as that of the source region is formed at the source and no lightly doped region is formed at the drain or the substrate at the drain is neutralized, or even a lightly doped region of the inverse conductive type as that of the drain region is formed at the drain, thus, regardless right reading or inverse reading, the turn-on current at reading the memory cell is smaller, so that better device performance can be achieved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1. A non-volatile memory, comprising:
- a first memory cell, formed on a first conductive type substrate, the first memory cell comprising: a gate, formed on the first conductive type substrate; a second conductive type drain region, formed in the first conductive type substrate at a first side of the gate; a charge storage layer, formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate; and a second conductive type first lightly doped region, formed in the first conductive type substrate at a second side of the gate, the second side being opposite to the first side.
2. The non-volatile memory as claimed in claim 1, wherein if the first conductive type is P-type, the second conductive type is N-type; if the first conductive is N-type, the second conductive type is P-type.
3. The non-volatile memory as claimed in claim 2, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
4. The non-volatile memory as claimed in claim 2, further comprising a second memory cell, the structure of the second memory cell being identical to the structure of the first memory cell, the second memory cell and the first memory cell being formed in symmetric manner and sharing the second conductive type first lightly doped region.
5. The non-volatile memory as claimed in claim 2, further comprising a second conductive type source region formed in the first conductive type substrate at the second side of the gate, wherein the second conductive type first lightly doped region is formed between the second conductive type source region and the gate.
6. The non-volatile memory as claimed in claim 5, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
7. The non-volatile memory as claimed in claim 5, further comprising a second memory cell, the structure of the second memory cell being identical to the structure of the first memory cell, the second memory cell and the first memory cell being formed in symmetric manner and sharing the second conductive type source region.
8. The non-volatile memory as claimed in claim 5, further comprising a first conductive type lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
9. The non-volatile memory as claimed in claim 8, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
10. The non-volatile memory as claimed in claim 8, further comprising a second memory cell, the structure of the second memory cell being identical to the structure of the first memory cell, the second memory cell and the first memory cell being formed in symmetric manner and sharing the second conductive type source region.
11. The non-volatile memory as claimed in claim 8, further comprising a second conductive type second lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
12. The non-volatile memory as claimed in claim 11, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
13. The non-volatile memory as claimed in claim 11, further comprising a second memory cell, the structure of the second memory cell being identical to the structure of the first memory cell, the second memory cell and the first memory cell being formed in symmetric manner and sharing the second conductive type source region.
14. The non-volatile memory as claimed in claim 1, further comprising a second dielectric layer formed between the charge storage layer and the first conductive type substrate and between the charge storage layer and the gate.
15. The non-volatile memory as claimed in claim 1, wherein the material of the charge storage layer comprises silicon nitride.
16. A non-volatile memory, comprising:
- a plurality of memory cells, formed on a first conductive type substrate and arranged as an array, each of the memory cells comprising: a gate, formed on the first conductive type substrate; a second conductive type drain region, formed in the first conductive type substrate at a first side of the gate; a charge storage layer, formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate; a second conductive type source region, formed in the first conductive type substrate at a second side of the gate, the second side being opposite to the first side; and a second conductive type first lightly doped region, formed between the second conductive type source region and the gate, wherein each of the memory cells shares the second conductive type source region or the second conductive type drain region with the adjacent memory cells in the same row;
- a plurality of source lines, arranged in parallel in the direction of columns, connecting the second conductive type source regions in the same column;
- a plurality of bit lines, arranged in parallel in the direction of rows, connecting the second conductive type drain regions in the same row;
- a plurality of word lines, arranged in parallel in the direction of columns, connecting the gates of the memory cells in the same column.
17. The non-volatile memory as claimed in claim 16, wherein if the first conductive type is P-type, the second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type.
18. The non-volatile memory as claimed in claim 16, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
19. The non-volatile memory as claimed in claim 16, further comprising a first conductive type lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
20. The non-volatile memory as claimed in claim 19, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
21. The non-volatile memory as claimed in claim 19, further comprising a second conductive type second lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
22. The non-volatile memory as claimed in claim 21, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
23. The non-volatile memory as claimed in claim 16, further comprising a second dielectric layer formed between the charge storage layer and the first conductive type substrate and between the charge storage layer and the gate.
24. The non-volatile memory as claimed in claim 16, wherein the material of the charge storage layer comprises silicon nitride.
25. A non-volatile memory, comprising:
- a plurality of memory cells, formed on a first conductive type substrate, arranged as an array, each of the memory cells comprising: a gate, formed on the first conductive type substrate; a second conductive type drain region, formed in the first conductive type substrate at a first side of the gate; a charge storage layer, formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate; a second conductive type source region, formed in the first conductive type substrate at a second side of the gate, the second side being opposite to the first side; and a second conductive type first lightly doped region, formed between the second conductive type source region and the gate, wherein the memory cells are connected in series in the direction of rows;
- a plurality of bit lines, arranged in parallel in the direction of columns, connecting the second conductive type drain regions or the second conductive type source regions in the same column;
- a plurality of word lines, arranged in parallel in the direction of rows, connecting the gates of the memory cells in the same row.
26. The non-volatile memory as claimed in claim 25, wherein if the first conductive type is P-type, the second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type.
27. The non-volatile memory as claimed in claim 25, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
28. The non-volatile memory as claimed in claim 25, further comprising a first conductive type lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
29. The non-volatile memory as claimed in claim 28, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
30. The non-volatile memory as claimed in claim 28, further comprising a second conductive type second lightly doped region formed in the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate.
31. The non-volatile memory as claimed in claim 30, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the first thickness is greater than the second thickness.
32. The non-volatile memory as claimed in claim 25, further comprising a second dielectric layer formed between the charge storage layer and the first conductive type substrate and between the charge storage layer and the gate.
33. The non-volatile memory as claimed in claim 25, wherein the material of the charge storage layer comprises silicon nitride.
Type: Application
Filed: Nov 9, 2006
Publication Date: May 17, 2007
Applicant: EMEMORY TECHNOLOGY INC. (Hsin-Chu)
Inventors: Shih-Chen Wang (Taipei City), Hsin-Ming Chen (Tainan County), Chun-Hung Lu (Yunlin), Ming-Chou Ho (Hsinchu City), Shih-Jye Shen (Hsinchu), Ching-Hsiang Hsu (Hsinchu City)
Application Number: 11/557,974
International Classification: H01L 29/788 (20060101);