SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.
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This application claims the priority benefit of U.S. provisional applications Ser. No. 60/597,210, filed on Nov. 17, 2005 and 60/743,630, filed on Mar. 22, 2006, all disclosures are incorporated therewith.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device which raises the limit of high-voltage stress and a method of fabricating the same.
2. Description of Related Art
A Metal Oxide Semiconductor (MOS) transistor device is one of the most important and fundamental electronic units among various electronic products. Since the invention of MOS transistor devices, people are constantly aiming for reducing the size of semiconductors; namely, more semiconductor devices are squeezed in a specific area so as to enhance and accelerate the performance of computation.
As the level of integration of integrated circuits increases, the dimensions of semiconductor devices decrease correspondingly. Accordingly, as the dimension of a Metal Oxide Semiconductor (MOS) transistor is reduced, the channel length also reduces. However, the dimension of the channel of a MOS transistor cannot be unlimitedly reduced. As the channel length of a semiconductor device reduces to a certain degree, various problems gradually emerge, which are generally so-called “short channel effects”. More specifically, when the channel length is decreased and the voltage applied remains unchanged, not only the operation speed of the transistor but also the lateral electric field in the channel is increased. Thereby, the energy of the channel electrons is increased, especially for the channel electrons near the drain region. The energy of these electrons is greater than the band gap of the semiconductor. Therefore, after colliding with valence-band electrons near the drain region, the channel electrons easily excite the valence-band electrons thereat to the conductive band and hot electrons are then formed. Parts of the hot electrons enter a gate oxide layer and cause damages, so that the reliability and the lifetime of the device are reduced. Especially when the dimension of a MOS transistor device is further reduced to a nanometer scale, the short channel effect and the punch through effect would become more serious, and a further size reduction of the semiconductor device is then hindered. Therefore, it is a common objective in the industry to produce a semiconductor device with small size, high integration, and high quality.
SUMMARY OF THE INVENTIONThis invention is to provide a semiconductor device and the method of fabricating the same. The semiconductor device has a simple structure and a high breakdown voltage so as to raise the limit of high-voltage stress and to be operated under high voltage.
This invention provides a semiconductor device, including a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on a first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed between the gate and the second conductive type source region.
According to an embodiment of the present invention, the first conductive type is a P-type while a second conductive type is an N-type. Conversely, the second conductive type is a P-type while the first conductive type is an N-type.
According to an embodiment of the present invention, the semiconductor device further includes a first dielectric layer. The first dielectric layer is formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at a side of the second conductive type source region and a second thickness at a side of the second conductive type drain region. The first thickness is larger than the second.
According to an embodiment of the present invention, the semiconductor device further includes a first conductive type lightly doped region. The first conductive type lightly doped region is formed between the gate and the second conductive type drain region.
According to an embodiment of the present invention, the semiconductor device further includes a second conductive type second lightly doped region. The second conductive type second lightly doped region is formed between the gate and the second conductive type drain region. The second conductive type first lightly doped region contains a different dopant concentration from the second conductive type second lightly doped region.
According to an embodiment of the present invention, the semiconductor device further includes insulating spacers. The insulating spacers are formed on the side walls of the gate.
According to an embodiment of the present invention, the material of the insulating spacers includes silicon nitride or silicon oxide.
Inasmuch as a lightly doped region having a same conductive type as the source region is formed between the source region and the gate, but no lightly doped region is formed between the drain region and the gate. Even forming a neutral substrate at the sides of the drain region or forming a lightly doped region with an opposite conductive type to the drain region at the sides of the drain region are two other alternatives for the semiconductor device of the present invention.
Thus, a high breakdown voltage is then provided to raise the limit of high-voltage stress of the MOS device and to operate the semiconductor device of the present invention under a high voltage.
The invention provides a method for fabricating a semiconductor device. The fabricating process is described below. First, a first conductive type substrate is provided, and a gate is formed on the first conductive type substrate. Then, a second conductive type first lightly doped region is formed in the substrate at a first side of the gate. Thereafter, a second conductive type source region is formed in the substrate at the first side of the gate, and a second conductive type drain region is formed at a second side of the gate, wherein the second conductive type first lightly doped region is formed in the first conductive type substrate between the second conductive type source region and the gate.
According to an embodiment of the present invention, the first conductive type is a P-type while a second conductive type is an N-type. Conversely, the first conductive type is an N-type while the second conductive type is a P-type.
According to an embodiment of the present invention, the method further includes a step of forming a first dielectric layer on the first conductive type substrate before the step of forming the gate on the first conductive type substrate.
According to an embodiment of the present invention, the first dielectric layer has a first thickness at a first side and a second thickness at a second side. The second thickness is larger than the first.
According to an embodiment of the present invention, the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate are provided as following. First, a patterned photoresist layer exposing the first conductive type substrate at the first side of the gate is formed on the substrate. An ion implantation process is then performed to form the second conductive type first lightly doped region. Afterward, the patterned photoresist layer is removed.
According to an embodiment of the present invention, the method further includes a step of forming a first conductive type lightly doped region in the substrate at the second side of the gate. The first conductive type lightly doped region is formed between the second conductive type drain region and the gate.
According to an embodiment of the present invention, the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate, and forming the first conductive type lightly doped region in the substrate at the second side of the gate are provided as following. First, a first patterned photoresist layer exposing the first conductive type substrate at the first side of the gate is formed on the substrate. A first ion implantation process is then performed to form the second conductive type first lightly doped region. After the first patterned photoresist layer is removed, a second patterned photoresist layer exposing the first conductive type substrate at the second side of the gate is formed on the substrate. A second ion implantation process is then performed to form the first conductive type lightly doped region, and the second patterned photoresist layer is removed.
According to an embodiment of the present invention, the method further includes forming a second conductive type second lightly doped region in the substrate at the second side of the gate. The second conductive type second lightly doped region is formed between the second conductive type drain region and the gate.
According to an embodiment of the present invention, the steps of forming the second conductive type first lightly doped region and the second conductive type second lightly doped region in the first conductive type substrate at the first and the second sides of the gate, and forming the first conductive type lightly doped region in the substrate at the second side of the gate are provided as following. First, a first ion implantation process is performed to form the second conductive type first lightly doped region and the second conductive type second lightly doped region. A patterned photoresist layer exposing the first conductive type substrate at the second side of the gate is then formed on the substrate. After a second ion implantation process is performed to form the first conductive type lightly doped region, the patterned photoresist layer is removed.
According to an embodiment of the present invention, the method further includes forming insulating spaces at the side walls of the gate.
The method of fabricating the semiconductor device of the present invention has a simple fabricating process which can be integrated with the fabricating process of a conventional Complementary Metal Oxide Semiconductor (CMOS) so as to reduce the time of fabricating the device. Various specific embodiments of the present invention are disclosed below, illustrating examples of various possible implementations of the concepts of the present invention. The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
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The gate 104 is, for example, formed on the first conductive type substrate 100. The material of the gate 104 is, for example, doped polysilicon.
The gate dielectric layer 102 is, for example, formed between the gate 104 and the first conductive type substrate 100. The material of the gate dielectric layer 102 is, for example, silicon oxide.
The second conductive type source region 110 and the second conductive type drain region 112 are formed in the first conductive type substrate 100 at both sides of the gate 104, for example.
The insulating spacers 108 are, for example, formed on the side walls of the gate 104. The material of the insulating spacers 108 is silicon oxide or silicon nitride, for example.
The second conductive type lightly doped region 114 is, for example, formed in the first conductive type substrate 100 between the gate 104 and the second conductive type source region 110. Namely, it is positioned under the insulating spacers 108.
In the above-mentioned embodiment, if the first conductive type is a P-type and the second conductive type is an N-type, the semiconductor device is an N-channel semiconductor device. On the other hand, if the first conductive type is an N-type and the second conductive type is a P-type, the semiconductor device is then a P-channel semiconductor device.
According to the semiconductor device of the present invention, inasmuch as the second conductive type lightly doped region is not formed at the sides of the second conductive type drain region 112, the limit of high-voltage stress of the MOS device can be raised, so that the semiconductor device of the present invention can be operated under a high voltage.
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Inasmuch as the lightly doped region having a same conductive type as the source region is formed between the source region and the gate, but no lightly doped region is formed between the drain region and the gate. Even forming a neutral substrate at the sides of the drain region or forming a lightly doped region with an opposite conductive type to the drain region at the sides of the drain region are two other alternatives for the semiconductor device of the present invention. Accordingly, a high breakdown voltage can be provided to raise the limit of the high-voltage stress of the MOS device and to operate the semiconductor device of the present invention under a high voltage.
The method of fabricating the semiconductor device in the present invention is explained thereupon.
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According to the method of fabricating the semiconductor device shown in
As stated above, the method of fabricating the semiconductor device of the present invention has a simple fabricating process which can be integrated with the process of fabricating a conventional Complementary Metal Oxide Semiconductor (CMOS) so as to reduce the time of fabricating the device.
In conclusion, inasmuch as a lightly doped region having a same conductive type as the source region is formed between the source region and the gate, but on lightly doped region is formed between the drain region and the gate. Even forming a neutral substrate at the sides of the drain region or forming a lightly doped region with an opposite conductive type to the drain region at the sides of the drain region are two other alternatives for the semiconductor device of the present invention. If the semiconductor device is operated under a smaller turned-on current, a better device performance can be then achieved and the limit of high-voltage stress can be raised so as to operate the semiconductor device of the present invention under a high voltage.
Furthermore, since the method of fabricating the semiconductor device of the present invention can be integrated with the process of fabricating a conventional Bipolar Complementary Metal Oxide Semiconductor (CMOS), the time of fabricating the device can be reduced without performing the photolithographic and etching processes.
The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.
Claims
1. A semiconductor device, comprising:
- a gate formed on a first conductive type substrate;
- a second conductive type drain region and a second conductive type source region, formed in the first conductive type substrate at both sides of the gate; and
- a second conductive type first lightly doped region formed between the gate and the second conductive type source region.
2. The semiconductor device of claim 1, wherein the first conductive type is a P-type while the second conductive type is an N-type; or the first conductive type is an N-type while the second conductive type is a P-type.
3. The semiconductor device of claim 2, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the side of the second conductive type source region and a second thickness at the side of the second conductive type drain region, and the first thickness is larger than the second thickness.
4. The semiconductor of claim 1, further comprising a first conductive type lightly doped region formed between the gate and the second conductive type drain region.
5. The semiconductor device of claim 4, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the side of the second conductive type source region and a second thickness at the side of the second conductive type drain region, and the first thickness is larger than the second thickness.
6. The semiconductor of claim 4, further comprising a second conductive type second lightly doped region formed between the gate and the second conductive type drain region.
7. The semiconductor device of claim 6, further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the side of the second conductive type source region and a second thickness at the side of the second conductive type drain region, and the first thickness is larger than the second thickness.
8. The semiconductor device of claim 6, wherein the second conductive type first lightly doped region has a dopant concentration different from the second conductive type second lightly doped region.
9. The semiconductor device of claim 1, further comprising insulating spacers formed at the side walls of the gate.
10. The semiconductor device of claim 9, wherein the material of the spacers comprises silicon nitride or silicon oxide.
11. A method of fabricating semiconductor device, comprising:
- providing a first conductive type substrate;
- forming a gate on the first conductive type substrate;
- forming a second conductive type first lightly doped region in the substrate at a first side of the gate; and
- forming a second conductive type source region in the substrate at the first side of the gate, and forming a second conductive type drain region at a second side of the gate, wherein the second conductive type first lightly doped region is formed in the first conductive type substrate between the second conductive type source region and the gate.
12. The method of fabricating semiconductor device of claim 11, wherein the first conductive type is a P-type while the second conductive type is an N-type; or the first conductive type is an N-type while the second conductive type is a P-type.
13. The method of fabricating semiconductor device of claim 11, further comprising forming a first dielectric layer on the first conductive type substrate before the step of forming the gate on the first conductive type substrate.
14. The method of fabricating semiconductor device of claim 13, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the second thickness is larger than the first thickness.
15. The method of fabricating semiconductor device of claim 11, wherein the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate comprise:
- forming a patterned photoresist layer exposing the first conductive type substrate at the first side of the gate on the substrate;
- performing an ion implantation process to form the second conductive type first lightly doped region; and
- removing the patterned photoresist layer.
16. The method of fabricating semiconductor device of claim 11, further comprising forming a first conductive type lightly doped region in the substrate at the second side of the gate, wherein the first conductive type lightly doped region is formed between the second conductive type drain region and the gate.
17. The method of fabricating semiconductor device of claim 16, wherein the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprise:
- forming a first patterned photoresist layer exposing the first conductive type substrate at the first side of the gate on the substrate;
- performing a first ion implantation process to form the second conductive type first lightly doped region;
- removing the first patterned photoresist layer;
- forming a second patterned photoresist layer exposing the first conductive type substrate at the second side of the gate on the substrate;
- performing a second ion implantation process to form the first conductive type lightly doped region; and
- removing the second patterned photoresist layer.
18. The method of fabricating semiconductor device of claim 16, further comprising: forming a second conductive type second lightly doped region in the substrate at the second side of the gate, wherein the second conductive type second lightly doped region is formed between the second conductive type drain region and the gate.
19. The method of fabricating semiconductor device of claim 18, wherein the steps of forming the second conductive type first lightly doped region and the second conductive type second lightly doped region in the first conductive type substrate at the first side and the second side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprise:
- performing a first ion implantation process to form the second conductive type first lightly doped region and the second conductive type second lightly doped region;
- forming a patterned photoresist layer exposing the first conductive type substrate at the second side of the gate on the substrate;
- performing a second ion implantation process to form the first conductive type lightly doped region; and
- removing the patterned photoresist layer.
20. The method of fabricating semiconductor device of claim 11, further comprising forming insulating spacers at the side walls of the gate.
Type: Application
Filed: Nov 7, 2006
Publication Date: May 17, 2007
Applicant: EMEMORY TECHNOLOGY INC. (Hsin-Chu)
Inventors: Shih-Chen Wang (Taipei City), Hsin-Ming Chen (Tainan County), Chun-Hung Lu (Yunlin), Ming-Chou Ho (Hsinchu City), Shih-Jye Shen (Hsinchu), Ching-Hsiang Hsu (Hsinchu City)
Application Number: 11/557,112
International Classification: H01L 31/00 (20060101);