Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.

Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component, obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.

Abstract: A method includes receiving an input that is in an electronic file format and that includes information associated with an integrated circuit (IC) layout, selecting a non EM rule compliant metal line of the IC layout that is in violation of an EM rule from the input, obtaining a current of the non EM rule compliant metal line from the input, comparing the current with a threshold current, and determining whether the EM rule violation is negligible based on the result of comparison. As such, a semiconductor device may be fabricated from the IC layout when it is determined that the EM rule violation is negligible.

Abstract: A method of designing a layout includes assigning a first color group to a plurality of first routing tracks. The method includes assigning a second color group to a plurality of second routing tracks. A first routing track is between adjacent second routing tracks. The method includes assigning a color from the first color group to each default conductive element along each first routing track. A color of a first default conductive element along each first routing track is different from a color of an adjacent default conductive element along a same first routing track. The method includes assigning a color from the second color group to each default conductive element along each second routing track. A color of a first default conductive element along each second routing track is different from a color of an adjacent default conductive element along a same second routing track.

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract: In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance.

Abstract: An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.

Abstract: Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power traces disposed in a second metal layer and parallel to a second direction that is perpendicular to the first direction, and third power traces disposed in the first metal layer parallel to the first direction. The first power traces arranged in the same straight line are separated from each other by a plurality of first gaps. The third power traces arranged in the same straight line are separated from each other by a plurality of second gaps. Each first gap is surrounded by the two adjacent third power traces. Each second gap is surrounded by the two adjacent first power traces. The first power traces are coupled to the third power traces via the second power traces.

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract: A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.

Abstract: In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.

Abstract: This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

Abstract: A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.