Patents by Inventor Chung-Hsing Wang
Chung-Hsing Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8547131Abstract: A system and method for observing threshold voltage variations are provided. A ring oscillator circuit comprises a plurality of inverters arranged in a sequential loop, a plurality of test circuits having devices under test, each coupled between a respective one of the inverters and a power supply. Each test circuit has a bypass field effect transistor (FET) having a first channel coupled between the power supply and a respective one of the inverters responsive to an individual enable signal, and a FET device under test having a second channel arranged in parallel to the first channel. A method is described for determining the threshold voltage of the device under test by disabling, for one of the inverters in the ring oscillator, the first FET device such that the device under test is coupled between the power supply and the respective inverter and affects the operating frequency of the ring oscillator.Type: GrantFiled: January 15, 2010Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsing Wang, Chih-Chieh Chen, Yi-Wei Chen
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Patent number: 8539396Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.Type: GrantFiled: March 9, 2012Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8504965Abstract: A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.Type: GrantFiled: September 30, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Yung-Chin Hou, Lie-Szu Juang
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Patent number: 8499274Abstract: A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.Type: GrantFiled: February 23, 2012Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ju Chao, Jerry Chang-Jui Kao, King-Ho Tam, Chung-Hsing Wang, Huan Chi Tseng
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Publication number: 20130174106Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.Type: ApplicationFiled: March 9, 2012Publication date: July 4, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung HSU, Huang-Yu CHEN, Chung-Hsing WANG
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Publication number: 20130154128Abstract: The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hsing Wang, King-Ho Tam, Huang-Yu Chen
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Publication number: 20130139120Abstract: A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.Type: ApplicationFiled: February 23, 2012Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ju Chao, Jerry Chang-Jui Kao, King-Ho Tam, Chung-Hsing Wang, Huan Chi Tseng
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Patent number: 8453095Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.Type: GrantFiled: July 6, 2011Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8448100Abstract: A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.Type: GrantFiled: April 11, 2012Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Lung Lin, Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao, Yi-Kan Cheng, Chin-Hsiung Hsu, Huang-Yu Chen, Yi-Chuin Tsai, Yuan-Te Hou, Chung-Hsing Wang
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Publication number: 20130091476Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.Type: ApplicationFiled: October 10, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huang-Yu CHEN, Yuan-Te HOU, Chung-Min FU, Chung-Hsing WANG, Wen-Hao CHEN, Yi-Kan CHENG
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Patent number: 8418117Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.Type: GrantFiled: July 7, 2010Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu
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Publication number: 20130069242Abstract: A semiconductor device structure for a three-dimensional integrated circuit has a semiconductor substrate having a plurality of through-substrate vias provided in the substrate, wherein three or more of the plurality of through-substrate vias are arranged in a hexagonal packing array with respect to their design-rule circle.Type: ApplicationFiled: September 20, 2011Publication date: March 21, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Yung YUH, Cheng-I Huang, Chung-Hsing Wang
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Patent number: 8359554Abstract: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.Type: GrantFiled: October 14, 2011Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsing Wang, Chih Sheng Tsai, Ying-Lin Liu, Kai-Yun Lin
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Publication number: 20130014070Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.Type: ApplicationFiled: July 6, 2011Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying SU, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8347132Abstract: A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.Type: GrantFiled: November 16, 2009Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chung-Hsing Wang, Myron Shak, Wei-Pin Changchien, Kuo-Yin Chen, Chi Wei Hu, Kevin Hung, Wu-An Kuo
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Patent number: 8307321Abstract: A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.Type: GrantFiled: March 22, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Chih-Chieh Chen, Jian-Yi Li
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Patent number: 8252489Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.Type: GrantFiled: June 24, 2011Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8239802Abstract: A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations.Type: GrantFiled: October 7, 2009Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Agrawal Aditya Binodkumar
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Patent number: 8232824Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.Type: GrantFiled: January 15, 2010Date of Patent: July 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsing Wang, Chih-Chieh Chen, Chih Sheng Tsai, Shu Yi Ying
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Publication number: 20120084745Abstract: A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Yung-Chin Hou, Lie-Szu Juang