Abstract: A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract: An I/O pad structure in an integrated circuit (IC) comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs.

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs.

Abstract: An embodiment method of streamlining parasitic modeling using a common device profile includes importing, using a processor, a simulated middle end of line (MEOL) profile into a characterization tool, generating, using the processor, a MEOL pattern based on the simulated MEOL profile, import, using the processor, the MEOL pattern and a real profile into a field solver to generate a MEOL capacitance table, updating, using the processor, capacitance data in the characterization tool based on the MEOL capacitance table generated, and generating, using the processor, a resistance and capacitance parasitic extraction technology file using the characterization tool with the capacitance data as updated.

Abstract: The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.

Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.