Patents by Inventor Chung-Hsing Wang

Chung-Hsing Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150113493
    Abstract: A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hung LIN, Chi Wei HU, Yuan-Te HOU, Chung-Hsing WANG, Chin-Chou LIU
  • Publication number: 20150091543
    Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.
    Type: Application
    Filed: June 4, 2014
    Publication date: April 2, 2015
    Inventors: Jerry Chang-Jui KAO, Chien-Ju Chao, Chin-Shen Lin, Nitesh Katta, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 8990762
    Abstract: A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Hung Yuh, Cheng-I Huang, Chung-Hsing Wang
  • Patent number: 8977991
    Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng
  • Publication number: 20150067624
    Abstract: A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: King-Ho TAM, Yeh-Chi CHANG, Kuo-Nan YANG, Zhe-Wei JIANG, Chung-Hsing WANG
  • Publication number: 20150035551
    Abstract: A method for cell characterization with Miller capacitance includes characterizing input capacitance of an input of a first stage in a cell by considering a first current transition at the input of the first stage up to a first stop time. The first stop time occurs during the first current transition exhibits a substantial tail portion contributed by the later of a first input voltage transition and a first output voltage transition reaching a corresponding steady state voltage. The first input voltage transition is associated with the input of the first stage. The first output voltage transition is associated with an output of the first stage coupled to the input through a capacitor.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: NITESH KATTA, JERRY CHANG-JUI KAO, KING-HO TAM, KUO-NAN YANG, CHUNG-HSING WANG
  • Patent number: 8937358
    Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Publication number: 20150012895
    Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng
  • Publication number: 20150001934
    Abstract: A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Jerry Chang-Jui KAO, Chien-Ju CHAO, Chou-Kun LIN, Chin-Shen LIN, King-Ho TAM, Kuo-Nan YANG, Chung-Hsing WANG
  • Patent number: 8914755
    Abstract: Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
  • Publication number: 20140359544
    Abstract: Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
  • Publication number: 20140351784
    Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 27, 2014
    Inventors: Meng-Xiang LEE, Li-Chung HSU, Shih-Hsien YANG, Ho Che YU, King-Ho TAM, Chung-Hsing WANG
  • Publication number: 20140298284
    Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 8847284
    Abstract: A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: 8850368
    Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng
  • Publication number: 20140282337
    Abstract: A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Hung YUH, Cheng-I HUANG, Chung-Hsing WANG
  • Publication number: 20140258952
    Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: 8826195
    Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang
  • Patent number: 8826212
    Abstract: A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yen Yeh, Yeh-Chi Chang, Yen-Pin Chen, Zhe-Wei Jiang, King-Ho Tam, Yuan-Te Hou, Chung-Hsing Wang
  • Publication number: 20140239412
    Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
    Type: Application
    Filed: April 30, 2013
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang