Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.

Abstract: The present disclosure relates to a wafer transfer robot having a robot blade that can be used to handle substrates that are patterned on both sides without causing warpage of the substrates. In some embodiments, the wafer transfer robot has a robot blade coupled to a transfer arm that varies a position of the robot blade. The robot blade has a wafer reception area that receives a substrate. Two or more spatially distinct contact points are located at positions along a perimeter of the wafer reception area that provide support to opposing edges of the substrate. The two or more contact points are separated by a cavity in the robot blade. The cavity mitigates contact between a backside of the substrate and the robot blade, while providing support to opposing sides of the substrate to prevent warpage of the substrate.

Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the spacer and overlying the top electrode.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with a sensing well having one or more sensing well spacers that reduce a size of the sensing well after its formation. In some embodiments, the integrated bio-sensor has a sensing device disposed within a semiconductor substrate. A dielectric structure is disposed onto a first side of the semiconductor substrate. The dielectric structure has an opening with a first width, which is exposed to an ambient environment and that overlies the sensing device. One or more sensing well spacers are arranged on sidewalls of the opening. The one or more sensing well spacers expose a bottom surface of the opening to define a sensing well having a second width that is smaller than the first width.

Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first opening in the first etch stop layer and the first dielectric layer. The method further comprises filling the first opening with a conductive material. The method additionally comprises forming a second etch stop layer and a second dielectric layer over the first etch stop layer. The method further comprises forming a second opening to expose the conductive material. The method additionally comprises forming a capacitor in the second opening and in contact with the conductive material.

Abstract: Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.

Abstract: A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first conductive layer, a cap dielectric layer, and a first electrode. The well has a predetermined doping type. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench between the first and second shoulder portions. The first trench has sidewalls and a bottom surface. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer.

Abstract: The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask.

Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer. The method further comprises filling the first trench with a conductive material. The method additionally comprises forming a second etch stop layer over the first etch stop layer. The method also comprises forming a second dielectric layer over the second etch stop layer. The method further comprises forming a second trench to expose the conductive material. The second trench is formed having a depth less than a total thickness of the first etch stop layer, the second etch stop layer and the second dielectric layer. The method additionally comprises depositing a first metal layer over sidewalls of the second trench and in contact with the conductive material.

Abstract: Embodiments of the present disclosure include a method for forming a semiconductor device, a method for forming a MISFET device, and a MISFET device. An embodiment is a method for forming a semiconductor device, the method including forming a source/drain over a substrate, forming a first etch stop layer on the source/drain, and forming a gate dielectric layer on the first etch stop layer and along the substrate. The method further includes forming a gate electrode on the gate dielectric layer, forming a second etch stop layer on the gate electrode, and removing the gate dielectric layer from over the source/drain.

Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract: The mechanisms for forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure also includes a first metal layer formed in the first dielectric layer and a magnetic layer formed over the first dielectric layer, and the magnetic layer has edges more than four in a cross section view.

Abstract: A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first conductive layer, a cap dielectric layer, and a first electrode. The well has a predetermined doping type. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench between the first and second shoulder portions. The first trench has sidewalls and a bottom surface. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer.

Abstract: A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.

Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.