Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security.

Abstract: An optical interconnect is provided which may allow flexible high-bandwidth interconnection between chips, eliminate the need for optical alignment between the optoelectrical (OE) die and waveguide during assembly because the OE die is at least partially embedded inside the waveguide (lower cladding layer, upper cladding layer, and core layer), eliminate the need for handling the optical interconnect at OEM, and not impact current substrate and motherboard technology.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.

Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.

Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Abstract: Some embodiments of the invention include a thermal interface between a heat spreader and a die. The thermal interface may include a main layer of a single material or a combination of multiple materials. The thermal interface may include one or more additional layers covering one or more surfaces of the main layer. The thermal interface may be bonded to the die and the heat spreader at a low temperature, with flux or without flux. Other embodiments are described and claimed.

Abstract: An optical connector module complete with optoelectronic devices, supporting integrated circuitry, and connector housing may be fabricated on a wafer level. A plurality of cavities may be formed on the backside of the wafer to accommodate an optoelectronic device. Active circuitry may be formed in a front side of the wafer. Through-vias electrically connect the front side to the back side. The backside of the wafer is overmolded with a polymer layer which when singulated into individual dies forms the plastic housing of an optical connector module.

Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

Abstract: In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter.

Abstract: Electronic assemblies and methods for forming assemblies including a diamond substrate are described. One embodiment includes providing a diamond support and forming a porous layer of SiO2 on the diamond support. A diamond layer is formed by chemical vapor deposition on the porous layer so that the porous layer is between the diamond support and the diamond layer. A polycrystalline silicon layer is formed on the diamond layer. The polycrystalline silicon layer is polished to form a planarized surface. A semiconductor layer is coupled to the polysilicon layer. After coupling the semiconductor layer to the polysilicon layer, the diamond support is detached from the diamond layer by breaking the porous layer. The semiconductor layer on the diamond layer substrate is then further processed to form a semiconductor device.

Abstract: An optical connector comprises a housing having a cavity extending there through to accept a mating connector. The connector comprises no optical components. Dummy solder bonding pads positioned on the connector allow the connector to be automated flip-chip bonded over a substrate waveguide.

Abstract: Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copper heat spreader. The heat spreader and the die are clamped together with the tin positioned between the heat spreader and the die. The assembly is heated so that the tin melts and forms at least one intermetallic compound with copper from the heat spreader. The heat spreader is then coupled to the die through the intermetallic compound.

Abstract: Methods and apparatus to mount an optical waveguide to a substrate are disclosed. A disclosed method involves providing a substrate having a first layer and a second layer. The first layer includes at least one alignment fiducial and the second layer covers the at least one fiducial. At least a portion of the second layer is removed to render the fiducial visible and a waveguide is automatically aligned with the first fiducial. The waveguide is then fixed to the substrate.

Abstract: A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.

Abstract: One embodiment includes a substrate having a plurality of dies and a support frame made of molding material which is molded between adjacent dies so as to join together and support adjacent dies. The embodiment further has a plurality of interconnects formed on selected die terminals and the molding material of the support frame joining adjacent dies. The interconnects may be formed utilizing a variety of techniques including those of the type used in conventional wafer fabrication techniques. Other embodiments are described and claimed.

Abstract: In one embodiment, a method comprises coupling a coreless substrate panel to a pressure cover plate of a carrier, applying flux to the coreless substrate panel, placing at least one die on the coreless substrate panel, reflowing solder onto the coreless substrate panel, defluxing the coreless substrate panel, underfilling the coreless substrate panel, and attaching at least one heat spreader to the coreless substrate panel.

Abstract: A method includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The mated first heat spreader and second heat spreader have at least one convection channel disposed therebetween. A process includes placing a first die in a first die recess of the first heat spreader, and placing a second die on a second die site on the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. A package is achieved by the method, with reduced thicknesses. The package can be coupled through a bumpless build-up layer. The package can be assembled into a computing system.