Patents by Inventor Daoqiang Lu

Daoqiang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7279720
    Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Ming Fang, Valery Dubin, Daoqiang Lu
  • Patent number: 7279359
    Abstract: Amine-based no-flow underfill materials and a method to produce flip-chip devices electrically bonded to a substrate are described. The no-flow underfill material includes an amine-based curing agent and a fluxing agent, which activates at a fluxing temperature and is neutral at the temperatures lower than the fluxing temperature. The fluxing agent of the no-flow underfill material heated to the activation temperature generates a reactive acid in-situ during chip attachment process to facilitate joint formation. The no-flow underfill material is formed on the substrate. A chip is placed on the no-flow underfill material formed on the substrate. A temperature is increased to activate the fluxing agent. The temperature is further increased to form conductive joints between the chip and the substrate. Further, the no-flow underfill material is cured. The conductive joints between the chip and the substrate may be lead-free.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Tian-An Chen, Daoqiang Lu
  • Publication number: 20070228112
    Abstract: A method of forming a microelectronic package, and an arrangement to attach a solder preform onto a microelectronic die in order to form the package. The method comprises: providing a reinforced solder preform including a solder preform and a backing layer attached to a backside of the solder preform; placing the reinforced solder preform on a surface of a first microelectronic component adapted to be soldered; attaching the solder preform to the surface of the first microelectronic component after placing the reinforced solder preform; removing the backing layer from the solder preform after placing the reinforced solder preform; placing a second microelectronic component to be soldered onto the solder preform after removing the backing layer; and soldering the second microelectronic component to the first microelectronic component to form the package.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Wei Shi, Thomas Fitzgerald, Steve Mayer, Carl Deppisch, Daoqiang Lu
  • Publication number: 20070223865
    Abstract: A coupler is passively aligned over a substrate, wherein the coupler is laterally aligned to an optoelectronic (OE) device coupled to the substrate. The coupler is placed on the substrate, wherein the coupler is vertically aligned to the OE device. The coupler is fixed to the substrate.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 27, 2007
    Inventors: Daoqiang Lu, Henning Braunisch, Bram Leader, Mark Trobough
  • Publication number: 20070218652
    Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.
    Type: Application
    Filed: May 9, 2007
    Publication date: September 20, 2007
    Inventors: Eric Li, Daoqiang Lu, Christopher Rumer, Paul Koning, Darcy Fleming, Gudbjorg Oskarsdottir, Tiffany Byrne
  • Patent number: 7256059
    Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Anna M. George, legal representative, Steven Towle, deceased
  • Patent number: 7251389
    Abstract: An apparatus and method for embedding a laser source on a semiconductor substrate and an optical interconnect to couple the laser source to internal components of the semiconductor substrate. An on-die waveguide is integrated on the semiconductor substrate. A package waveguide is disposed on the semiconductor substrate and evanescently coupled to the on-die waveguide. The laser source is embedded within the packaged waveguide to provide an optical signal to the on-die waveguide via the package waveguide.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: July 31, 2007
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Bruce A. Block, Dongming He
  • Publication number: 20070158807
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One embodiment includes an electronic device having a first die, the first die having a top surface, a bottom surface, and a plurality of side surfaces. The first die also includes a plurality of metal pads on the top surface extending to an outer edge of the top surface, and a plurality of metal pads on the bottom surface extending to an outer edge of the bottom surface. The first die also includes a plurality of metal regions along the side surfaces, wherein each of the metal regions extends between one of the metal pads on the top surface and one of the metal pads on the bottom surface. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 12, 2007
    Inventors: Daoqiang Lu, Wei Shi, Qing Zhou, Jiangqi He
  • Publication number: 20070152328
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps, comprises a solder. The method also includes forming a metal region including indium and tin, on at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps. The method also includes positioning the first metal bumps on the second metal bumps, and heating the metal bumps and the metal region and melting the solder. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Susheel Jadhav, Daoqiang Lu, Nitin Deshpande
  • Publication number: 20070155198
    Abstract: A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security.
    Type: Application
    Filed: December 22, 2005
    Publication date: July 5, 2007
    Inventors: Wei Shi, Daoqiang Lu, Qing Zhou, Jiangqi He
  • Publication number: 20070152321
    Abstract: The formation of electronic assemblies including a heat spreader coupled to at least one die is described. One embodiment relates to a method including positioning a solder on a heat spreader. The method also includes forming a solid state diffusion bond between the solder and the heat spreader. The solid state diffusion bonded solder and heat spreader are positioned on a die and heated to a temperature sufficient to melt the solder and form a bond between the solder and the die, in the absence of a flux. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Wei Shi, Daoqiang Lu, Qing Zhou, Jiangqi He
  • Patent number: 7238605
    Abstract: An apparatus including a contact point formed on a device layer of a circuit substrate or an interconnect layer on the substrate; a first dielectric material; and a different second polymerizable dielectric material on the substrate and separated from the device layer or the interconnect layer by the first dielectric material following polymerization, the second dielectric material comprising a glass transition temperature of at least 250° C. and a thermal decomposition temperature of at least 400° C. A method including depositing a dielectric material and thermally treating the dielectric material at a temperature greater than the thermal decomposition temperature.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventor: Daoqiang Lu
  • Patent number: 7236666
    Abstract: Optical apparatus, methods of forming the apparatus, and methods of using the apparatus are disclosed herein. In one aspect, an optical apparatus may include a substrate, an on-substrate microlens coupled with the substrate to receive light from an off-substrate light emitter and focus the light toward a focal point, and an on-substrate optical device coupled with the substrate proximate the focal point to receive the focused light. Communication of light in the reverse direction is also disclosed. Systems including the optical apparatus are also disclosed.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Anna George, legal representative, Henning Braunisch, Daoqiang Lu, Gilroy J. Vandentop, Steven Towle, deceased
  • Publication number: 20070138647
    Abstract: A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.
    Type: Application
    Filed: December 21, 2005
    Publication date: June 21, 2007
    Inventors: Qing Zhou, Wei Shi, Jiangqi He, Daoqiang Lu
  • Publication number: 20070140627
    Abstract: An optical-electrical interface for interfacing optical signals with electrical signals. The optical-electrical interface includes an alignment interface for receiving an external waveguide connector from a first side. The alignment interface includes an alignment structure to mate with a corresponding alignment structure of the external waveguide connector to passively align the external waveguide connector. A first microlens is disposed on the first side of the alignment interface. A second microlens is disposed on a second side of the alignment interface. An optical path passes through the alignment interface between the first microlens and the second microlens. A conductor is disposed on the second side of the alignment interface.
    Type: Application
    Filed: December 21, 2005
    Publication date: June 21, 2007
    Inventor: Daoqiang Lu
  • Publication number: 20070132106
    Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.
    Type: Application
    Filed: December 12, 2005
    Publication date: June 14, 2007
    Inventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
  • Publication number: 20070127865
    Abstract: Optical devices and methods for constructing the same are disclosed. An example optical device includes an optical transmitter, a photodetector and a waveguide optically coupling the optical transmitter and the photodetector. It also includes a substrate having a first cavity to receive the optical transmitter and a second cavity to receive the second transmitter. The first and second cavities are located and dimensioned to passively align the optical transmitter, the waveguide and the photodetector when the transmitter is inserted into the first cavity and the photodetector is inserted into the second cavity.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 7, 2007
    Inventors: Daoqiang Lu, Gilroy Vandentop
  • Publication number: 20070126118
    Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 7, 2007
    Inventors: Daoqiang Lu, Henning Braunisch
  • Patent number: 7226812
    Abstract: Methods and apparatuses for wafer support and release using sacrificial materials in wafer processing. In one embodiment, a solution of a sacrificial polymer is spray-coated on the wafer bump side to form a thin layer of the sacrificial polymer after solvent vaporization. An adhesive layer is then used to attach the wafer bump side onto a wafer support substrate over the sacrificial polymer to support the wafer in backside processing. After wafer thinning and backside metal deposition, the wafer is exposed to heat to thermally decompose the sacrificial polymer into gases. The decomposition of the sacrificial polymer reduces the adhesion of the adhesive layer to the bump side of the wafer such that, when the support substrate is detached from the wafer, the adhesive layer is detached together with the support substrate from the wafer bump side, leaving almost no residual traces.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Anna M. George, legal representative, Steven Towle, deceased
  • Patent number: 7220622
    Abstract: Disclosed are embodiments of a method of attaching a die to a substrate and a heat spreader to the die in a single heating operation. A number of conductive bumps extending from the die may also be reflowed during this heating operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Susheel G. Jadhav, Daoqiang Lu