Abstract: A microelectronic die assembly. The die assembly includes a microelectronic die, and a thermally conductive element attached to the backside of the die with a thermal interface material. The thermally conductive element has lateral dimensions smaller than, substantially equal to, or larger than lateral dimensions of the die by up to a maximum amount, wherein the maximum amount is adapted to allow a mounting of the die assembly to a package substrate.

Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Abstract: A method for aligning at least two photonic components over an interposer, and an optical package that may align such components. The method may include providing an interposer; fabricating electrical conductors passing from one surface of the interposer to an opposite surface of the interposer at selected contact positions; soldering the photonic components over the selected contact positions on the first surface, while allowing solder self-alignment. Other embodiments are described and claimed.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Abstract: An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: An adhesive adapted with particular optical properties, and its use to couple a substrate to a substrate holder during substrate processing are disclosed. After processing the substrate, the optical properties of the adhesive may be exploited to locate and/or remove adhesive residue that may be present on the substrate.

Abstract: In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: An optical connector module complete with optoelectronic devices supporting integrated circuitry, and connector housing may be fabricated on a wafer level. A plurality of cavities may be formed on the backside of the wafer to accommodate an optoelectronic device. Active circuitry may be formed in a front side of the wafer. Through-vias electrically connect the front side to the back side. The backside of the wafer is overmolded with a polymer layer which when singulated into individual dies forms the plastic housing of an optical connector module.

Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps, comprises a solder. The method also includes forming a metal region including indium and tin, on at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps. The method also includes positioning the first metal bumps on the second metal bumps, and heating the metal bumps and the metal region and melting the solder. Other embodiments are described and claimed.

Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.

Abstract: A method of making a microelectronic package. The method includes: providing a carrier; providing a tacky pad on the carrier; placing a die onto the tacky pad such that an active surface of the die adheres to the tacky pad, bonding an IHS onto a backside of the die after placing to form a die-IHS combination, removing the die-IHS combination from the tacky pad; and mounting the die-IHS combination onto a package substrate to form the package.

Abstract: A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.

Abstract: Methods of forming microelectronic device structures are described. Those methods may include placing a plurality of support rings onto a tacky layer of a support carrier, wherein the support rings are disposed within a cavity of the support carrier; placing a plurality of thin die onto a pedestal of the support carrier, wherein a top surface of the thin die is substantially flush with at top surface of the support ring; and then building up layers on the top surface of the die.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect structure, removing a portion of the anisotropic conductive layer to expose at least one of the compliant conductive spheres; and then attaching a second substrate to the anisotropic conductive layer.

Abstract: An optical interconnect is provided which may allow flexible high-bandwidth interconnection between chips, eliminate the need for optical alignment between the optoelectrical (OE) die and waveguide during assembly because the OE die is at least partially embedded inside the waveguide (lower cladding layer, upper cladding layer, and core layer), eliminate the need for handling the optical interconnect at OEM, and not impact current substrate and motherboard technology

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a conformal layer of a water soluble nanopowder on a wafer, and then scribing the wafer.