Patents by Inventor Daoqiang Lu

Daoqiang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WAFER-LEVEL ASSEMBLY OF HEAT SPREADERS FOR DUAL IHS PACKAGES
    Publication number: 20090034206
    Abstract: An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.
    Type: Application
    Filed: October 7, 2008
    Publication date: February 5, 2009
    Applicant: Intel Corporation
    Inventors: Daoqiang Lu, Rajashree Baskaran, Chuan Hu
  • Wafer-level assembly of heat spreaders for dual IHS packages
    Patent number: 7476568
    Abstract: An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: January 13, 2009
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Rajashree Baskaran, Chuan Hu
  • LOW TEMPERATURE THERMAL INTERFACE MATERIALS
    Publication number: 20090001556
    Abstract: A method may provide thermal interface material. The method comprises providing a first coating layer on a top side of a base metal layer and a second coating layer on a bottom side of the base metal layer, wherein the coating layer has a melting point lower than a melting point of the base metal layer; attaching the base metal layer to a die and a heat spreader; and melting the first coating layer and the second coating layer to bond to the die and the heat spreader.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Haixiao Sun, Daoqiang Lu
  • Reducing input capacitance for high speed integrated circuits
    Publication number: 20080316662
    Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Xiang Yin Zeng, Ming Dong Cui, Gregory V. Christensen, Mostafa Naguib Abdulla, Daoqiang Lu, Jiangqi He, Jiamiao Tang
  • MULTI-DIE MOLDED SUBSTRATE INTEGRATED CIRCUIT DEVICE
    Publication number: 20080277781
    Abstract: One embodiment includes a substrate having a plurality of dies and a support frame made of molding material which is molded between adjacent dies so as to join together and support adjacent dies. The embodiment further has a plurality of interconnects formed on selected die terminals and the molding material of the support frame joining adjacent dies. The interconnects may be formed utilizing a variety of techniques including those of the type used in conventional wafer fabrication techniques. Other embodiments are described and claimed.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Inventors: Haixiao SUN, Daoqiang LU, Aiying XU
  • WAFER-LEVEL BONDING FOR MECHANICALLY REINFORCED ULTRA-THIN DIE
    Publication number: 20080265407
    Abstract: An embodiment of the present invention is a technique to fabricate a package. A metal sheet having trenches is formed. A thinned wafer supported by a wafer support substrate (WSS) is formed. The metal sheet is bonded to the WSS-supported thinned wafer to form a metal bonded thinned wafer. The thinned wafer is diced to the trenches into die assemblies.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 30, 2008
    Applicant: Intel Corporation
    Inventors: Daoqiang Lu, John Tang
  • Wafer-level bonding for mechanically reinforced ultra-thin die
    Patent number: 7435664
    Abstract: An embodiment of the present invention is a technique to fabricate a package. A metal sheet having trenches is formed. A thinned wafer supported by a wafer support substrate (WSS) is formed. The metal sheet is bonded to the WSS-supported thinned wafer to form a metal bonded thinned wafer. The thinned wafer is diced to the trenches into die assemblies.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, John Tang
  • Integrated micro-channels for 3D through silicon architectures
    Patent number: 7432592
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: Wei Shi, Daoqiang Lu, Yiqun Bai, Qing A. Zhou, Jiangqi He
  • ADHESIVE WITH DIFFERENTIAL OPTICAL PROPERTIES AND ITS APPLICATION FOR SUBSTRATE PROCESSING
    Publication number: 20080216950
    Abstract: An adhesive adapted with particular optical properties, and its use to couple a substrate to a substrate holder during substrate processing are disclosed. After processing the substrate, the optical properties of the adhesive may be exploited to locate and/or remove adhesive residue that may be present on the substrate.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Inventors: Daoqiang Lu, Eric J. Li
  • SOLDER DEPOSITION ON WAFER BACKSIDE FOR THIN-DIE THERMAL INTERFACE MATERIAL
    Publication number: 20080191358
    Abstract: A solder is deposited on the backside of a wafer. The wafer can be predeposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat spreader that did not require a pre-deposited solder.
    Type: Application
    Filed: June 29, 2007
    Publication date: August 14, 2008
    Inventor: Daoqiang Lu
  • Apparatus and method for attaching a semiconductor die to a heat spreader
    Patent number: 7407085
    Abstract: Embodiments of an apparatus and method for attaching a semiconductor die to a heat spreader (or other thermal component) are disclosed. The apparatus includes a substantially flat surface to receive a number of die, and the die may be held in place on the surface by a flux, the flux being subsequently removed prior to bonding. The apparatus may further include a number of registration elements to hold a heat spreader in a relative position over each die. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: August 5, 2008
    Assignee: Intel Corporation
    Inventors: Jadhav G. Susheel, Daoqiang Lu
  • Assembly of thin die coreless package
    Publication number: 20080160673
    Abstract: In one embodiment, a method comprises coupling a coreless substrate panel to a pressure cover plate of a carrier, applying flux to the coreless substrate panel, placing at least one die on the coreless substrate panel, reflowing solder onto the coreless substrate panel, defluxing the coreless substrate panel, underfilling the coreless substrate panel, and attaching at least one heat spreader to the coreless substrate panel.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Daoqiang Lu, Rajashree Baskaran, Charan Gurumurthy
  • CURVED HEAT SPREADER DESIGN FOR ELECTRONIC ASSEMBLIES
    Publication number: 20080157345
    Abstract: The formation of electronic assemblies is described. One embodiment relates to an electronic assembly including a die coupled to a substrate, the die including a curved surface. The assembly also includes a thermal interface material having a first curved surface and a second curved surface, the first curved surface coupled to the curved surface of the die. The assembly also includes a heat spreader having a curved surface, wherein the curved surface of the heat spreader is coupled to the second curved surface of the thermal interface material. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Daoqiang LU, Wei SHI
  • Double side stacked die package
    Publication number: 20080157322
    Abstract: A method of forming a package, comprising providing a set of dies on a substrate. The substrate may have a first die on its upper side and a second die on its lower side. A first interconnect may be provided in the substrate, wherein the first interconnect penetrates through the substrate to couple the dies to the substrate.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Jia Miao Tang, Xiang Yin Zeng, Daoqiang Lu, Jiangqi He
  • Adhesive with differential optical properties and its application for substrate processing
    Patent number: 7393468
    Abstract: An adhesive adapted with particular optical properties, and its use to couple a substrate to a substrate holder during substrate processing are disclosed. After processing the substrate, the optical properties of the adhesive may be exploited to locate and/or remove adhesive residue that may be present on the substrate.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 1, 2008
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Eric J. Li
  • BREAKABLE INTERCONNECTS AND STRUCTURES FORMED THEREBY
    Publication number: 20080153207
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect structure, removing a portion of the anisotropic conductive layer to expose at least one of the compliant conductive spheres; and then attaching a second substrate to the anisotropic conductive layer.
    Type: Application
    Filed: March 7, 2008
    Publication date: June 26, 2008
    Applicant: INTEL CORPORATION
    Inventors: Daoqiang Lu, Henning Braunisch
  • Tubular-shaped bumps for integrated circuit devices and methods of fabrication
    Publication number: 20080142964
    Abstract: An integrated circuit die includes one or more tubular-shaped conductive bumps disposed on one side thereof. The tubular-shaped bumps may comprise copper, and may be used for input/output (I/O) signaling. The die may also include solid bumps for I/O and/or power delivery. The tubular-shaped bumps are relatively more compliant than the solid bumps, and may alleviate the effects of thermally induced stresses. Other embodiments are described and may be claimed.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Inventors: Haixiao Sun, Daoqiang Lu
  • Chip-to-chip optical interconnect
    Patent number: 7373033
    Abstract: A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Jiamiao Tang, Jiangqi He, Edward A. Zarbock
  • Methods and apparatus to optically couple an optoelectronic chip to a waveguide
    Patent number: 7372120
    Abstract: Methods and apparatus to optically couple an optoelectronic chip to a waveguide are disclosed. A disclosed apparatus includes a substrate, a waveguide mounted on the substrate and an optoelectronic chip bonded to the substrate and having an optical element directly engaging the waveguide.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Anna M. George, legal representative, Daoqiang Lu, Henning Braunisch, Gilroy Vandentop, Steven Towle
  • ELECTRONIC ASSEMBLIES HAVING A LOW PROCESSING TEMPERATURE
    Publication number: 20080096324
    Abstract: Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copper heat spreader. The heat spreader and the die are clamped together with the tin positioned between the heat spreader and the die. The assembly is heated so that the tin melts and forms at least one intermetallic compound with copper from the heat spreader. The heat spreader is then coupled to the die through the intermetallic compound.
    Type: Application
    Filed: December 14, 2007
    Publication date: April 24, 2008
    Inventors: Daoqiang LU, Chuan Hu