Patents by Inventor Daoqiang Lu

Daoqiang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DUAL-CHIP INTEGRATED HEAT SPREADER ASSEMBLY, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME
    Publication number: 20080079144
    Abstract: A method includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The mated first heat spreader and second heat spreader have at least one convection channel disposed therebetween. A process includes placing a first die in a first die recess of the first heat spreader, and placing a second die on a second die site on the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. A package is achieved by the method, with reduced thicknesses. The package can be coupled through a bumpless build-up layer. The package can be assembled into a computing system.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Jiamiao Tang, Daoqiang Lu, Jiangqi He, Xiang Yin Zeng
  • Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same
    Publication number: 20080079125
    Abstract: A microelectronic die assembly. The die assembly includes a microelectronic die, and a thermally conductive element attached to the backside of the die with a thermal interface material. The thermally conductive element has lateral dimensions smaller than, substantially equal to, or larger than lateral dimensions of the die by up to a maximum amount, wherein the maximum amount is adapted to allow a mounting of the die assembly to a package substrate.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Daoqiang Lu, Chuan Hu, Dongming He
  • Integrated circuit package to provide high-bandwidth communication among multiple dice
    Patent number: 7348678
    Abstract: A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Qing A. Zhou, Wei O. Shi, Jiangqi He, Daoqiang Lu
  • Microelectronic package, method of manufacturing same, and system containing same
    Publication number: 20080067668
    Abstract: A microelectronic package includes a substrate (110), a die (120) electrically connected to the substrate, and a heat dissipation device (130) coupled to the die. The heat dissipation device includes a capacitor (250, 310). In one embodiment the heat dissipation device is a microchannel having a base (131) and a cover plate (132, 300) over the base, and the capacitor is located within the cover plate.
    Type: Application
    Filed: September 15, 2006
    Publication date: March 20, 2008
    Inventors: Wei Shi, Daoqiang Lu, Qing Zhou, Jiangoi He
  • Optical interconnect with passive optical alignment
    Patent number: 7344318
    Abstract: A coupler is passively aligned over a substrate, wherein the coupler is laterally aligned to an optoelectronic (OE) device coupled to the substrate. The coupler is placed on the substrate, wherein the coupler is vertically aligned to the OE device. The coupler is fixed to the substrate.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Henning Braunisch, Bram Leader, Mark B. Trobough
  • Split socket optical interconnect
    Patent number: 7344383
    Abstract: A split microprocessor socket is disclosed that provides a cavity created at an outer edge of the microprocessor socket. An optical module may be fitted in the cavity thus providing an optical fiber or waveguide connection directly to the socket. This low cost optical interconnect, closely packaged with the microprocessor, may alleviate bandwidth constraints associated with conventional electrical connections.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Andrew C. Alduino, Henning Braunisch
  • DUAL HEAT SPREADER PANEL ASSEMBLY METHOD FOR BUMPLESS DIE-ATTACH PACKAGES, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME
    Publication number: 20080054448
    Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 6, 2008
    Inventors: Daoqiang Lu, Jiangqi He, Xian Yin Zeng, Jiamiao Tang
  • Passively aligned optical-electrical interface with microlenses
    Patent number: 7334946
    Abstract: An optical-electrical interface for interfacing optical signals with electrical signals. The optical-electrical interface includes an alignment interface for receiving an external waveguide connector from a first side. The alignment interface includes an alignment structure to mate with a corresponding alignment structure of the external waveguide connector to passively align the external waveguide connector. A first microlens is disposed on the first side of the alignment interface. A second microlens is disposed on a second side of the alignment interface. An optical path passes through the alignment interface between the first microlens and the second microlens. A conductor is disposed on the second side of the alignment interface.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventor: Daoqiang Lu
  • Electronic assemblies having a low processing temperature
    Patent number: 7319048
    Abstract: Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copper heat spreader. The heat spreader and the die are clamped together with the tin positioned between the heat spreader and the die. The assembly is heated so that the tin melts and forms at least one intermetallic compound with copper from the heat spreader. The heat spreader is then coupled to the die through the intermetallic compound.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: January 15, 2008
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Chuan Hu
  • Wafer-level bonding for mechanically reinforced ultra-thin die
    Publication number: 20080003720
    Abstract: An embodiment of the present invention is a technique to fabricate a package. A metal sheet having trenches is formed. A thinned wafer supported by a wafer support substrate (WSS) is formed. The metal sheet is bonded to the WSS-supported thinned wafer to form a metal bonded thinned wafer. The thinned wafer is diced to the trenches into die assemblies.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Daoqiang Lu, John Tang
  • Wafer-level assembly of heat spreaders for dual IHS packages
    Publication number: 20080003719
    Abstract: An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Daoqiang Lu, Rajashree Baskaran, Chuan Hu
  • Detachable stiffener for ultra-thin die
    Publication number: 20080003780
    Abstract: A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer is mounted onto a stiffener. The WSS is released from the thin wafer. The thin wafer and the stiffener are diced into a plurality of stiffener-reinforced dice.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Haixiao Sun, Daoqiang Lu
  • ELECTRONIC ASSEMBLY WITH STACKED IC'S USING TWO OR MORE DIFFERENT CONNECTION TECHNOLOGIES AND METHODS OF MANUFACTURE
    Publication number: 20080003717
    Abstract: An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Qing A. Zhou, Daoqiang Lu, Wei Shi, Jiangqi He
  • Heat spreader as mechanical reinforcement for ultra-thin die
    Publication number: 20080001268
    Abstract: A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventor: Daoqiang Lu
  • CHIP-TO-CHIP OPTICAL INTERCONNECT
    Publication number: 20070297713
    Abstract: A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via.
    Type: Application
    Filed: June 13, 2006
    Publication date: December 27, 2007
    Inventors: Daoqiang Lu, Jiamiao Tang, Jiangqi He, Edward A. Zarbock
  • METHOD, APPARATUS, AND SYSTEM FOR THIN DIE THIN THERMAL INTERFACE MATERIAL IN INTEGRATED CIRCUIT PACKAGES
    Publication number: 20070284730
    Abstract: Some embodiments of the invention include a thermal interface between a heat spreader and a die. The thermal interface may include a main layer of a single material or a combination of multiple materials. The thermal interface may include one or more additional layers covering one or more surfaces of the main layer. The thermal interface may be bonded to the die and the heat spreader at a low temperature, with flux or without flux. Other embodiments are described and claimed.
    Type: Application
    Filed: June 12, 2006
    Publication date: December 13, 2007
    Inventors: Wei Shi, Daoqiang Lu, Edward A. Zarbock
  • Microelectronic devices having underfill materials with improved fluxing agents
    Patent number: 7303944
    Abstract: Microelectronic packages formed by using novel fluxing agents are disclosed. In one aspect, a microelectronic package may include a microelectronic device, a substrate, and an interconnect structure including a solder material coupling the microelectronic device with the substrate. Underfill material may be included around the interconnect structure between the microelectronic device and the substrate. The underfill material may include an organic rosin acid moiety derived from an anhydride adduct of a rosin compound that was used as a fluxing agent. Methods of making such microelectronic packages using anhydride adducts of rosin compounds are also disclosed.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventors: Tian-An Chen, Daoqiang Lu
  • Solder deposition on wafer backside for thin-die thermal interface material
    Patent number: 7288438
    Abstract: A solder is deposited on the backside of a wafer. The wafer can be pre-deposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat spreader that did not require a pre-deposited solder.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventor: Daoqiang Lu
  • Optical package
    Patent number: 7283699
    Abstract: Optical packages are disclosed. In one aspect, an optical package may include a surface, a microelectronic device coupled with the surface, a first waveguide coupled with the microelectronic device, a second waveguide having a first end that is evanescently coupled with the first waveguide and a second end, a first thickness of a cladding material disposed between the second end and the surface, and a second thickness of a cladding material disposed between the first end and the first waveguide. The first thickness may be greater than the second thickness. Methods of making the optical packages are also disclosed. Apparatus and methods of aligning operations on optical packages are also disclosed.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Henning Braunisch, Gilroy Vandentop
  • Semiconductor wafer coat layers and methods therefor
    Patent number: 7279362
    Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne