Abstract: Techniques for video manipulation using a product card within a short-form video environment are disclosed. Display is accomplished using a video stream interface that can be executed on an electronic device associated with a user. The video stream, such as a short-form video or livestream video, can include one or more products. The display shows product cards associated with the products within the video. The product cards originate from a repository, a third-party website, or some other source. The product information includes text, video, and/or audio content. The user is provided an option to purchase one or more of the products presented within the video by selecting the product card. The viewer selects product cards displayed in front of the video to learn more about the products and/or purchase the products.

Abstract: A neuron device including: an antiferromagnetic pinning layer, a first ferromagnetic layer and a spin orbit coupling layer formed on a substrate in sequence; a free layer formed on the spin orbit coupling layer and moving a magnetic domain wall according to a spin orbit torque; a tunneling layer formed on the free layer; a left pinning layer and a right pinning layer formed on two sides of the free layer and having opposite magnetization directions; and a reference layer formed on the tunneling layer; wherein the free layer, the tunneling layer and the reference layer constitute a magnetic tunnel junction, and the magnetic tunnel junction is configured to read neuronal signals. Also provided is a method for preparing a neuron device based on a spin orbit torque.

Abstract: A computer device includes a processor configured to simulate a virtual environment based on a set of virtual environment parameters, and perform ray tracing to render a view of the simulated virtual environment. The ray tracing includes generating a plurality of rays for one or more pixels of the rendered view of the simulated virtual environment. The processor is further configured to determine sub-pixel data for each of the plurality of rays based on intersections between the plurality of rays and the simulated virtual environment, and store the determined sub-pixel data for each of the plurality of rays in an image file.

Abstract: Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.

Abstract: A composite hydrogel sponge and its preparation method and application, and a solar desalination device are provided. The composite hydrogel sponge includes a water supply layer and an evaporation layer disposed on the water supply layer. A material of the water supply layer is polyacrylamide hydrogel, and a material of the evaporation layer is polyacrylamide/graphene composite hydrogel. The polyacrylamide/graphene composite hydrogel includes the polyacrylamide hydrogel and the graphene dispersed in the polyacrylamide hydrogel. The composite hydrogel sponge has a special porous structure of the sponge, which is beneficial to the rapid transmission and supply of water; meanwhile, the graphene on the surface of the evaporation layer can fully receive solar energy to achieve higher photo-thermal conversion efficiency.

Abstract: A memory device is provided. The memory device includes a semiconductor substrate, a tunneling layer, a floating gate electrode, a dielectric layer, and a control gate electrode. The semiconductor substrate has an active region. The tunneling layer is over the active region of the semiconductor substrate. The floating gate electrode is over the tunneling layer. The floating gate electrode has a first portion and a second portion electrically connected to the first portion. The dielectric layer is over the floating gate electrode. The control gate electrode is over the dielectric layer. The control gate electrode has a first portion interposed between the first and second portions of the floating gate electrode.

Abstract: An array substrate and a liquid crystal display panel thereof. The array substrate includes a substrate having a plurality of pixel regions arranged in an array. Each of the pixel regions (120a) includes: a first electrode, a second electrode, an insulation protrusion, and a reflection electrode. An electric field is fit to form between the second electrode and the first electrode, and an electric field is also fit to form between the reflection electrode and the second electrode. The second electrode includes a slit electrode, which includes a plurality of slit portions and a plurality of electrode portions each arranged between adjacent slit portions. The electrode portion at least includes a first strip-shaped portion and a second strip-shaped portion. An extension direction of the first strip-shaped portion intersects with that of the second strip-shaped portion, and the first strip and second strip-shaped portions of each electrode portion are connected at a corresponding bending portion.

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure comprises a memory cell comprising: a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact coupled to a word line and surrounding a first portion of the insulating layer, and multiple plate line contact segments coupled to multiple plate lines respectively and surrounding a second portion of the insulating layer. The memory structure further comprises a bit line contact coupled to a bit line and coupled to a first end of the cylindrical body, a source line contact coupled to a source line, and a source cap coupled between the source line contact and a second end of the cylindrical body to increase a distance between the source line contact and the plate line contact segments.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and a third gate contact configured to control electrical charge conduction between the first gate contact and the second gate contact. The 3D memory device can utilize dynamic flash memory (DFM), increase storage efficiency, provide tri-gate control, provide different programming options, increase read, program, and erase operation rates, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

Abstract: The present disclosure provides a thermostat applied to a heating, ventilation and air conditioning (HVAC) system including: a memory storing machine executable instructions; one or more processors, wherein when the machine executable instructions are executed, the one or more processors are configured to perform the following operations: obtaining device information of the HVAC system, and region information of a user's location; according to the device information of the HVAC system and the region information, in response to an energy saving mode and a schedule selected by the user, determining a predicted energy consumption and a reference energy consumption; and determining energy saving amount according to the predicted energy consumption and the reference energy consumption.

Abstract: Disclosed in the present invention is hyperspectral image classification method based on context-rich networks. The method comprises a training stage and a prediction stage, wherein the training stage comprises image pre-processing, sample selection and network training. Firstly, performing normalization on a hyperspectral image, and then randomly selecting an appropriate proportion of marked samples from each category to generate a label map, and performing training by using the designed network; in the prediction stage, directly inputting the whole image into the trained network and obtaining a final classification result. By means of the present invention, data pre-processing, feature extraction, the process of context-rich information capturing, and classification are taken into comprehensive consideration in the whole flow; and the classification of a hyperspectral image is realized by means of constructing an end-to-end network.

Abstract: Systems and apparatuses include a controller including at least one processor coupled to a memory storing instructions that, when executed by the at least one processor, causes the at least one processor to: receive data indicative of at least one of a current route or of a current performance of a vehicle; correlate at least one of the current route or the current performance to a control strategy; and determine at least one of a timing or a duration of an active regeneration event for an aftertreatment system based on the correlated control strategy.

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

Abstract: A method for preparing a carbon nano tube/polyacrylic acid hydrogel, a product and an application thereof are provided. The method includes: oxidizing a carbon nanotube into a carboxylated carbon nanotube, thereafter performing in-situ polymerization with acrylic acid, sodium hydroxide, ammonium persulfate, triethanolamine and N, N-methylenebisacrylamide to obtain a carbon nanotube/polyacrylic acid hydrogel. The hydrogel has a uniform porous structure, facilitating a rapid transmission and supply of water. The carbon nanotubes in the hydrogel are of an array structure, achieving a full absorption of solar energy to realize a high-efficiency photothermal conversion. The gel is attached to a sponge base to obtain a solar-powered carbon nano tube/polyacrylic acid hydrogel steam generator for the photothermal conversion. The steam generator is used for solar seawater desalination, but can improve evaporation rate and evaporation efficiency.

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact coupled to the memory cell, and a source line coupled to the source line contact. The memory cell comprises a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact surrounding a first portion of the insulating layer, the word line contact coupled to a word line, and a plurality of plate line contact segments surrounding a second portion of the insulating layer, the plurality of plate line contact segments coupled to a common plate line.