Patents by Inventor Dinesh Somasekhar

Dinesh Somasekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell
    Publication number: 20090166701
    Abstract: In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the first insulating layer therebelow. The first trench is filed with a polymer. A third insulating layer is formed over the polymer. A second trench is formed in the third insulating layer, wherein the second trench is above the first trench and extends laterally therefrom. The polymer is removed from the first trench. A capacitor is formed within the first and the second trenches.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Brian S. Doyle, Dinesh Somasekhar, Robert S. Chau
  • Sense amplifier method and arrangement
    Patent number: 7532528
    Abstract: A memory system having a selectable configuration for sense amplifiers is included. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Muhammad M Khellah, Yibin Ye, Nam Sung Kim, Vivek K De
  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology
    Patent number: 7514746
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Brian Doyle, Suman Datta, Vivek K. De
  • MEMORY CIRCUIT WITH ECC BASED WRITEBACK
    Publication number: 20090083495
    Abstract: Provided herein are circuits incorporating a dynamic technique to minimize power overhead with writeback. In some embodiments, error-correction-code (ECC) is used to dynamically detect bit failures and use that information to identify memory sub-sections to be enabled for writeback.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Vivek K. De
  • Asymmetric memory cell
    Patent number: 7501316
    Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • SENSE AMPLIFIER METHOD AND ARRANGEMENT
    Publication number: 20090003108
    Abstract: In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
    Type: Application
    Filed: June 30, 2007
    Publication date: January 1, 2009
    Inventors: Dinesh Somasekhar, Muhammad M. Khellah, Yibin Ye, Nam Sung Kim, Vivek K. De
  • Isolation of MIM FIN DRAM capacitor
    Publication number: 20090001438
    Abstract: In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a silicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating layer.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Brian S. Doyle, Dinesh Somasekhar, Robert S. Chau, Suman Datta
  • FLOATING BODY MEMORY ARRAY
    Publication number: 20090003050
    Abstract: Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
    Type: Application
    Filed: June 30, 2007
    Publication date: January 1, 2009
    Inventors: Uygar E. Avci, Peter L.D. Chang, Dinesh Somasekhar
  • Capacitor, method of increasing a capacitance area of same, and system containing same
    Publication number: 20080237675
    Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Brian S. Doyle, Roberts S. Chau, Suman Datta, Vivek De, Ali Keshavarzi, Dinesh Somasekhar
  • On-chip memory cell and method of manufacturing same
    Publication number: 20080237678
    Abstract: An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: Suman Datta, Jack T. Kavalieros, Brian S. Doyle, Dinesh Somasekhar, Ali Keshavarzi
  • Increasing the surface area of a memory cell capacitor
    Publication number: 20080237796
    Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Brian S. Doyle, Robert S. Chau, Vivek De, Suman Datta, Dinesh Somasekhar
  • High density memory
    Publication number: 20080237672
    Abstract: In one embodiment of the invention, a method of forming a semiconductor device includes forming a dynamic random access memory using spacer-defined lithography.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Brian S. Doyle, Dinesh Somasekhar, Robert Chau
  • SRAM device having forward body bias control
    Patent number: 7423899
    Abstract: A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Vivek K. De, James W. Tschanz
  • Memory with dynamically adjustable supply
    Patent number: 7403426
    Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Fatih Hamzaoglu, Kevin Zhang, Nam Sung Kim, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Vivek K. De, Bo Zheng
  • Memory cell bit valve loss detection and restoration
    Publication number: 20080162986
    Abstract: For one disclosed embodiment, an apparatus may comprise a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also comprise first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Nam Sung Kim, Muhammad Khellah, Yibin Ye, Dinesh Somasekhar, Vivek De
  • Memory having bit line with resistor(s) between memory cells
    Publication number: 20080158932
    Abstract: For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Inverter based return-to-zero (RZ)+ Non-RZ (NRZ) signaling
    Publication number: 20080152356
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Dinesh Somasekhar, Sourav Saha, Gregory E. Ruhl, Ashoke Ravi
  • 2-transistor floating-body dram
    Patent number: 7391640
    Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Signal generating circuit
    Publication number: 20080143407
    Abstract: Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Fabrice Paillet, Peter Hazucha, Sung Tae Moon, Tanay Karnik
  • Memory circuit
    Patent number: 7385865
    Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Gunjan H. Pandya, Vivek K. De