Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract: For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments are also disclosed.

Abstract: A memory line driver system may include a first input line to receive a clock-gated signal associated with a first supply power level, a second input line to receive an information signal associated with a second supply power level, and an output to drive a memory cell line according to the first supply power level based on the clock-gated signal and the information signal.

Abstract: Architectures including digital outphasing transmitters.

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.

Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.

Abstract: A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

Abstract: A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.

Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.

Abstract: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

Abstract: A level shifting device comprises an input stage, a cascode stage, a cross-coupled stage, and an output stage. The input stage may receive a data signal or binary logic input in a first data range, a complement of the data signal, and a first voltage. The cascode stage may receive a first voltage and may be connected to the input stage. The cross-coupled stage may be adapted to isolate the first voltage and may be connected to the cascode stage. The output stage may receive a second voltage, provide an output, and be connected to the cross-coupled stage. The cascode stage may be adapted to provide the first voltage as the output when the logic input is a first value and provide the second voltage as the output when the logic input is a second value. Other embodiments are also claimed and described.

Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.