Patents by Inventor Dinesh Somasekhar

Dinesh Somasekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitor structure for a logic process
    Publication number: 20070004162
    Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Memory circuit
    Publication number: 20070002607
    Abstract: In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De
  • Memory cell driver circuits
    Publication number: 20060291265
    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Dinesh Somasekhar, Yibin Ye, Ali Keshavarzi, Muhammad Khellah, Vivek De
  • APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY
    Publication number: 20060285393
    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De, Tanay Karnik
  • Purge-based floating body memory
    Publication number: 20060279985
    Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 14, 2006
    Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De, Gerhard Schrom
  • Memory with dynamically adjustable supply
    Publication number: 20060268626
    Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: May 25, 2005
    Publication date: November 30, 2006
    Inventors: Fatih Hamzaoglu, Kevin Zhang, Nam Kim, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, Bo Zheng
  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology
    Publication number: 20060267093
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 30, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Brian Doyle, Suman Datta, Vivek De
  • Reducing power consumption in integrated circuits
    Publication number: 20060262610
    Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
    Type: Application
    Filed: May 23, 2005
    Publication date: November 23, 2006
    Applicant: Intel Corporation
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, James Tschanz, Stephen Tang
  • 1P1N 2T gain cell
    Patent number: 7123500
    Abstract: A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi, Shih-Lien L. Lu, Vivek K. De
  • Two transistor gain cell, method, and system
    Patent number: 7120072
    Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad M Khellah, Fabrice Paillet, Stephen H Tang, Ali Keshavarzi, Shih-Lien L Lu, Vivek K De
  • Crosspoint memory array utilizing one time programmable antifuse cells
    Patent number: 7110278
    Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
  • Gating for dual edge-triggered clocking
    Patent number: 7109776
    Abstract: Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Dinesh Somasekhar, Vivek K. De
  • Overvoltage detection apparatus, method, and system
    Patent number: 7102358
    Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H Tang, Mohsen Alavi, Vivek K De
  • OTP antifuse cell and cell array
    Patent number: 7102951
    Abstract: Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology
    Patent number: 7098507
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Brian Doyle, Suman Datta, Vivek K. De
  • 2-Transistor floating-body dram
    Publication number: 20060187706
    Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
    Type: Application
    Filed: February 22, 2005
    Publication date: August 24, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Floating point multiply accumulator
    Patent number: 7080111
    Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: July 18, 2006
    Assignee: Intel Corporation
    Inventors: Amaresh Pangal, Dinesh Somasekhar, Shekhar Y. Borkar, Sriram R. Vangal
  • Apparatus and method for a one-phase write to a one-transistor memory cell array
    Patent number: 7075821
    Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 11, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Gerhard Schrom, Vivek K. De
  • Floating-body DRAM with two-phase write
    Patent number: 7072205
    Abstract: A row of floating-body single transistor memory cells is written to in two phases.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • One time programmable memory
    Publication number: 20060139995
    Abstract: A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De