Patents by Inventor Ding Wang

Ding Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package Substrates, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
    Publication number: 20180204815
    Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Hao-Cheng Hou, Yu-Feng Chen, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Substrate design for semiconductor packages and method of forming same
    Patent number: 10026671
    Abstract: An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chien-Hsun Lee, Tsung-Ding Wang, Jung Wei Cheng, Ming-Che Liu, Hao-Cheng Hou, Hung-Jen Lin
  • OPTICAL FIBER WITH BRAGG GRATING AND THIN FILM COATING AND CONNECTOR
    Publication number: 20180196191
    Abstract: An article comprises an optical fiber having a first end with a first end surface having a multilayer thin film filter coating deposited thereon, a second end with a second end surface, and a fiber Bragg grating formed within the optical fiber between the first and second ends.
    Type: Application
    Filed: July 7, 2016
    Publication date: July 12, 2018
    Inventors: Ding Wang, Raman K. Selli
  • Dam for three-dimensional integrated circuit
    Patent number: 10020236
    Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductar Manufacturing Campany
    Inventors: Tsung-Ding Wang, An-Jhih Su, Chien Ling Hwang, Jung Wei Cheng, Hsin-Yu Pan, Chen-Hua Yu
  • OPTICAL FIBER WITH THIN FILM COATING AND CONNECTOR
    Publication number: 20180172914
    Abstract: An article comprises an optical fiber having a first end with a first end surface having a deposited coating only on a portion thereon. The first end can have a frustoconic or tronconic shape. The optical fiber can be utilized as a stub fiber in an optical device, such as an optical connector, receptacle or adapter. The deposited coating can be a wavelength selective multilayer thin film coating. The deposited coating can reflect a selected wavelength of light back to a central office to provide monitoring in a communication network, such as a PON.
    Type: Application
    Filed: May 5, 2016
    Publication date: June 21, 2018
    Inventors: Daniel J. Treadwell, Donald K. Larson, Ding Wang, William J. Clatanoff, Manfred Bauer, Johannes Fink
  • Method of forming a semiconductor device including strain reduced structure
    Patent number: 9997480
    Abstract: A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Tsung-Yuan Yu, Yu-Feng Chen, Tsung-Ding Wang
  • Package-on-package structure and methods for forming the same
    Patent number: 9985013
    Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Jung Wei Cheng, Hao-Cheng Hou, Tsung-Ding Wang, Jiun Yi Wu, Ming-Chung Sung
  • Semiconductor device packages and methods
    Patent number: 9935038
    Abstract: Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tsung-Ding Wang, Hung-Jen Lin, Jiun Yi Wu, Mirng-Ji Lii, Chien-Hsun Lee
  • Substrate design for semiconductor packages and method of forming same
    Patent number: 9935090
    Abstract: An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jung Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee
  • Device with optimized thermal characteristics
    Patent number: 9929115
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a molding compound surrounding the semiconductor substrate, the conductive pad and the conductor. In the semiconductor device, the conductor has a stud shape.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hao-Cheng Hou, Jung Wei Cheng, Tsung-Ding Wang, Ming-Che Liu
  • Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices
    Patent number: 9917068
    Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hao-Cheng Hou, Yu-Feng Chen, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Apparatus and method of measuring six degrees of freedom
    Patent number: 9903934
    Abstract: A dimensional measuring device sends a beam of light to a remote probe having a retroreflector and a pitch/yaw sensor. The pitch/yaw sensor passes the light through an aperture and a lens to a position sensor that generates an electrical signal indicative of the position of the received light. A processor uses the electrical signal to determine a pitch angle and a yaw angle of the remote probe.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 27, 2018
    Assignee: FARO TECHNOLOGIES, INC.
    Inventors: Mathieu Antoina, Lawrence B. Brown, Jonathan R. Day, Matthew Frederick Evans, Ricardo Martins, Jacob J. Mertz, John Mountney, Robert Mark Neal, James Schloss, Quintin Stotts, Ding Wang, Robert E. Bridges
  • Transceiver interface having staggered cleave positions
    Patent number: 9897763
    Abstract: The disclosure generally relates to sets of optical waveguides such as optical fiber ribbons, and fiber optic connectors useful for connecting multiple optical fibers such as in optical fiber ribbon cables. In particular, the disclosure provides an efficient, compact, and reliable optical fiber connector that incorporates an optically transmissive substrate combining the features of optical fiber alignment, along with redirecting and shaping of the optical beam.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 20, 2018
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: James R. Bylander, Ding Wang
  • METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING STRAIN REDUCED STRUCTURE
    Publication number: 20180047686
    Abstract: A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 15, 2018
    Inventors: Hsien-Wei CHEN, Ying-Ju CHEN, Tsung-Yuan YU, Yu-Feng CHEN, Tsung-Ding WANG
  • Packages with Die Stack Including Exposed Molding Underfill
    Publication number: 20180033775
    Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
  • System in package process flow
    Patent number: 9881898
    Abstract: A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co.,Ltd.
    Inventors: Tsung-Ding Wang, Chien-Hsun Lee
  • PACKAGE ASSEMBLY
    Publication number: 20180012860
    Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsiun Lee, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Methods of Forming Multi-Die Package Structures Including Redistribution Layers
    Publication number: 20180005984
    Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Tsung-Ding Wang, Chien-Hsun Lee
  • Method of forming 3D integrated circuit package with panel type lid
    Patent number: 9859266
    Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Kim Hong Chen, Jung Wei Cheng, Chien Ling Hwang, Hsin-Yu Pan, Han-Ping Pu
  • Package structures and methods of forming the same
    Patent number: 9859267
    Abstract: Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution structure from the first die. A second encapsulant is on the redistribution structure and at least laterally encapsulates the second die. The second encapsulant has a surface distal from the redistribution structure. A conductive feature extends from the redistribution structure through the second encapsulant to the surface of the second encapsulant. A conductive pillar is on the conductive feature, and the conductive pillar protrudes from the surface of the second encapsulant.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Cheng Hou, Ming-Che Liu, Chun-Chih Chuang, Jung Wei Cheng, Tsung-Ding Wang, Hung-Jen Lin