Abstract: A package includes a printed circuit board (PCB), and a die bonded to the PCB through solder balls. A re-workable underfill is dispensed in a region between the PCB and the die.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region.

Abstract: A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Abstract: Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a packaged semiconductor device. An encapsulant is formed over the IC dies and between the neighboring IC dies. The encapsulant and the IC dies are planarized to expose contacts on top surfaces of the IC dies, and redistribution layers (RDLs) are formed over the planarized encapsulant and the planarized IC dies. Openings are formed in a topmost dielectric layer of the RDLs to expose interconnects in the RDL, and a conductive seed layer is formed over the RDL and in the openings. Connectors of a first type and connectors of a second type are formed over the seed layer in the openings. The packaged semiconductor device is diced into individual IC packages.

Abstract: Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces.

Abstract: The disclosure generally relates to sets of optical waveguides such as optical fiber ribbons, and fiber optic connectors useful for connecting multiple optical fibers. In particular, the disclosure provides an efficient, compact, and reliable optical fiber connector that incorporates a unitary substrate comprising a plurality of staggered light redirecting features on an input surface thereof directing incoming light from optical fibers through the substrate towards optical elements to be coupled with.

Abstract: Disclosed is a method for determining the turnover rate of biomolecules in a subject, which include administering to the subject, 2H20 in an amount sufficient to label biomolecules in the subject with 2H. Samples are collected from the subject at one or more time points and isotopomers are detected for the labeled biomolecules in the samples. The fractional abundance is determined for the isotopomers of the biomolecules in the samples and the biomolecule turnover rates of the one or more labeled biomolecules is determined based on the fractional abundance of the isotopomers. A computer-implemented method is also disclosed for determining the turnover rate of one or more biomolecules in subject. In certain other embodiments, a system for determining protein turnover rates in a subject is also provided. Also provided in certain embodiments is a computer program product for determining protein turnover rates in a subject.

Abstract: The disclosure generally relates to sets of optical waveguides such as optical fiber ribbons and embedded optical waveguides, and optical interconnects useful for connecting multiple optical waveguides such as in optical fiber ribbon cables and printed circuit boards (PCBs) having optoelectronic capabilities. In particular, the disclosure provides an efficient, compact, and reliable optical waveguide connector that incorporates microlenses and re-directing elements which combine the features of optical waveguide alignment, along with redirecting and shaping of the optical beam.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.

Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.

Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Abstract: The disclosure generally relates to sets of optical waveguides such as optical fiber ribbons and embedded optical waveguides (132a-d), and optical interconnects useful for connecting multiple optical waveguides such as in optical fiber ribbon cables and printed circuit boards having optoelectronic capabilities. In particular, the disclosure provides an efficient, compact, and reliable optical waveguide connector (100) that incorporates microlenses and re-directing elements (136a-d) which combine the features of optical waveguide alignment, along with redirecting and shaping of the optical beam.

Abstract: A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

Abstract: An optical fiber connector for terminating a fiber cable comprising a plurality of optical fibers, comprises an outer connector housing, a ferrule essentially free of adhesive, a backbone, and a collar body disposed between the ferrule and backbone. The collar body includes a remote gripping region to remotely grip the plurality of optical fibers outside of the ferrule. In some aspects, the collar body includes a fiber comb portion that separates potentially tangled fibers, arranges the plurality of fibers in a uniform pitch, and provides for straightforward feeding of the fiber array into ferrule bores during a fiber cable insertion process. In some aspects, the connector includes a resilient element disposed between the backbone and a rear portion of the collar body, and an intermediate spring element disposed between a front portion of the collar body and a rear portion of the ferrule.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.