Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby.

Abstract: A method for hoisting and transporting assemblies in an underground nuclear power plant, the method including: 1) pouring concrete onto a reactor cavern to form a rock anchor beam; hoisting a circular bridge crane to the reactor cavern through a hoist shaft on a top of the reactor cavern; mounting the circular bridge crane on the rock anchor beam by using a truck crane; 2) installing a containment cylinder and a track beam of a polar crane in the reactor cavern using the circular bridge crane; hoisting a gantry crane on one end of a polar crane girder and sending the polar crane girder to the reactor cavern; hoisting the other end of the polar crane girder using the circular bridge crane; allowing the polar crane girder to be horizontal; and mounting the polar crane girder on the track beam.

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

Abstract: A latching structure includes a first plate, a second plate and a sliding plate disposed on a surface of the first plate and movable in a first direction. The first plate includes first arches each having an alignment hole in the first direction. The second plate includes second arches each having a latching hole in the first direction. The sliding plate includes pins corresponding to the latching holes. When the alignment hole accommodates the second arch and the sliding plate is located at a latching position, the pin is located in a corresponding latching hole to block separation of the first plate from the second plate in a second direction. When the sliding plate is located at a retracted position, the pin separates from the corresponding latching hole to allow separation of the first plate from the second plate in the second direction.

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

Abstract: In a network, communications between nodes in the network can be routed along different communication pathways. The network can include subnetworks provided and administered by third parties, and can include virtual private networks (VPNs), so that the different pathways can be or include VPN tunnels that pass through different subnetworks of the communications network. A central controller can monitor performance of the pathways, including those not in primary use, and dynamically adjust routing of communications traffic between the nodes by directing communication traffic to specific pathways or tunnels. The controller can direct different types of traffic (for example, data, voice) to particular pathways, and can direct traffic to different pathways based on direction of traffic flow (for example, uplink along one pathway and downlink along another pathway).

Abstract: A latching structure includes a first plate, a second plate and a sliding plate disposed on a surface of the first plate and movable in a first direction. The first plate includes first arches each having an alignment hole in the first direction. The second plate includes second arches each having a latching hole in the first direction. The sliding plate includes pins corresponding to the latching holes. When the alignment hole accommodates the second arch and the sliding plate is located at a latching position, the pin is located in a corresponding latching hole to block separation of the first plate from the second plate in a second direction. When the sliding plate is located at a retracted position, the pin separates from the corresponding latching hole to allow separation of the first plate from the second plate in the second direction.

Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.

Abstract: A heat-dissipating device configured to cool the battery pack of an electric vehicle includes a coolant circulating pump and a tank. The coolant circulating pump is configured to engage with the one or more heat dissipation pipes of the electric vehicle and communicate with the one or more heat dissipation pipes. The tank is configured to contain coolant which includes phase change material. When cooling is required, for example during battery recharging, the coolant circulating pump is configured to inject the coolant in the tank into the one or more heat dissipation pipes via the coolant inlet, drive the coolant to flow in the one or more heat dissipation pipes, and take the coolant out from the one or more heat dissipation pipes via the coolant outlet to the exterior. A related electric vehicle and a related heat dissipation method are also provided.

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

Abstract: Provided herein are devices, systems, and methods for conducting electrophoresis. The devices, systems, and methods are suited for portability, low power consumption, integrated operation, and remote monitoring.

Abstract: A construction layout for caverns of an underground nuclear power plant, including: two primary caverns accommodating nuclear reactor powerhouses, electric powerhouse caverns, safe powerhouse caverns, auxiliary powerhouse caverns, nuclear fuel powerhouse caverns, connecting powerhouse caverns, a first primary traffic tunnel, a third primary traffic tunnel, a second primary traffic tunnel, a fourth primary traffic tunnel, and a primary steam channel. The electric powerhouse caverns, the safe powerhouse caverns, and the nuclear fuel powerhouse caverns are arranged along the longitudinal direction of the mountain. Each of the safe powerhouse caverns and each of the nuclear fuel powerhouse caverns are disposed on two sides of each of the two primary caverns in the longitudinal direction of the mountain, respectively. Each of the electric powerhouse caverns and each of the safe powerhouse caverns are located on a same side of each the two primary caverns.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: Electrochemical Impedance Spectroscopy (EIS) is used in conjunction with continuous glucose monitors and continuous glucose monitoring (CGM) to enable in-vivo sensor calibration, gross (sensor) failure analysis, and intelligent sensor diagnostics and fault detection. An equivalent circuit model is defined, and circuit elements are used to characterize sensor behavior.

Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.

Abstract: A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.