Patents by Inventor Fei Yu

Fei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • In-vivo electrochemical impedance spectroscopy (EIS)-based calibration
    Patent number: 10321844
    Abstract: Electrochemical Impedance Spectroscopy (EIS) is used in conjunction with continuous glucose monitors and continuous glucose monitoring (CGM) to enable in-vivo sensor calibration, gross (sensor) failure analysis, and intelligent sensor diagnostics and fault detection. An equivalent circuit model is defined, and circuit elements are used to characterize sensor behavior.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 18, 2019
    Assignee: MEDTRONIC MINIMED, INC.
    Inventors: Andrea Varsavsky, Fei Yu, Michael E. Miller, Ning Yang
  • Techniques providing metal gate devices with multiple barrier layers
    Patent number: 10312236
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING ISOLATION STRUCTURES WITH LINERS
    Publication number: 20190157156
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a first fin and a second fin over a substrate, and conformally forming a silicon oxide layer over the first fin using a first atomic layer deposition (ALD) process. The method also includes conformally forming a silicon nitride layer over the silicon oxide layer using a second ALD process, and forming an insulating layer to fill the trench between the first fin and the second fin over the substrate. The method further includes recessing the insulating layer, the silicon oxide layer, and the silicon nitride layer to form an isolation structure with a liner. In addition, the method includes forming a gate structure over the first fin, and forming a source region and a drain region in the first fin and on opposite sides of the gate structure.
    Type: Application
    Filed: April 27, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Ju CHEN, Xiong-Fei YU, Chi-On CHUI, Yee-Chia YEO, Huicheng CHANG
  • SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20190148141
    Abstract: Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Inventors: Chun-Heng CHEN, Hong-Fa Luan, Xiong-Fei Yu, Hui-Cheng Chang, Chia-Wei Hsu
  • SEMICONDUCTOR DEVICES, FINFET DEVICES AND METHODS OF FORMING THE SAME
    Publication number: 20190140082
    Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shieling layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yuan Chang, Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
  • Shift register unit and method for driving the same, gate drive circuit and display device
    Patent number: 10283038
    Abstract: A shift register unit and a method for driving the shift register unit, a gate drive circuit and a display device are provided. The shift register unit includes a driving signal generating module and a selecting module. The driving signal generating module generates a driving signal for driving n rows of gate lines to be turned on, a duration of the driving signal being equal to a duration spent on scanning the n rows of gate lines, and n is equal to or greater than 2. The selecting module, connected to the driving signal generating module and input terminals of the n rows of gate lines, selects the n rows of gate lines sequentially and connects each selected gate line to the driving signal generating module, such that the driving signal is inputted to the n rows of gate lines sequentially.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 7, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD, HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaoliang Zhou, Hongwei Wang, Fei Yu, Lei Jiang
  • FinFET doping methods and structures thereof
    Patent number: 10276399
    Abstract: A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack at least partially over a fin extending from a substrate. In various embodiments, a barrier metal layer is deposited over the gate stack. By way of example, a thermal fluorine treatment is performed, where the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and where the fluorinated layer includes a plurality of fluorine atoms. In some embodiments, after forming the fluorinated layer, an anneal is performed to drive at least some of the plurality of fluorine atoms into the gate stack (e.g., into the interfacial layer and the high-K dielectric layer), thereby conformally doping the gate stack with the at least some of the plurality of fluorine atoms.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Xiong-Fei Yu, Chia-Wei Hsu
  • Fin field effect transistors having conformal oxide layers and methods of forming same
    Patent number: 10269921
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chia-Cheng Chen, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang, Meng-Shu Lin
  • ELECTRONIC DEVICE AND CONTROL METHOD THEREOF
    Publication number: 20190114024
    Abstract: An electronic device includes a touch detection unit that detects a touch operation executed on an operation surface, a pressure detection unit that detects a pressing force of the touch operation, and a control unit that controls executing a different function based on the detected pressing force of the touch operation when the touch operation is detected by the touch detection unit. In a case where a touch operation is detected again within a predetermined period from a previous touch operation after the control unit has controlled a function based on the pressing force to be executed based on the touch operation, the control unit controls a same function as the function executed based on the previous touch operation to be executed regardless of the pressing force.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 18, 2019
    Inventor: Fei Yu
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20190115348
    Abstract: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yuan CHANG, Xiong-Fei YU, Hui-Cheng CHANG
  • Multiple gate field effect transistors having oxygen-scavenged gate stack
    Patent number: 10263091
    Abstract: A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chih Chieh Yeh, Chih-Hsin Ko, Cheng-Hsien Wu, Liang-Yin Chen, Xiong-Fei Yu, Yen-Ming Chen, Chan-Lon Yang
  • Controller and control method for alternating current contactor
    Patent number: 10256063
    Abstract: A controller for an alternating current contactor includes: a filtering and rectification circuit that filters and rectifies external alternating current; an electromagnet component driven by an output of the filtering and rectification circuit that performs actions of attraction, holding or releasing; a power transistor circuit connected to the electromagnet component; and a microcontroller that controls the power transistor circuit to control the actions performed by the electromagnet component. The controller further includes a voltage control loop that provides a voltage feedback signal and a current control loop that provides a current feedback signal to the microcontroller. The microcontroller generates a control signal according to the voltage feedback signal.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 9, 2019
    Assignees: SEARI ELECTRIC TECHNOLOGY CO., LTD., ZHEJIANG CHINT ELECTRICS CO., LTD.
    Inventors: Fei Yu, Changxun Gu, Shunfeng Ge, Di Zhang, Yugang Feng, Yawen Shi, Ping Zeng
  • Data Synchronization Method and Out-of-Band Management Device
    Publication number: 20190079675
    Abstract: A data synchronization method includes checking first to-be-checked information stored in an active area of a first board to obtain a first check result and second to-be-checked information stored in an active area of a second board to obtain a second check result before data synchronization, where the first board and the second board are include in an out-of-band management device, determining an active board and a standby board from the first board and the second board according to the first check result and the second check result, and synchronizing data in an active area of the active board to a standby area of the standby board. Hence, the method can be implemented to ensure validity of data synchronization.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Fei Yu, Chaojun Jiang
  • Methods and apparatus for a substrate core layer
    Patent number: 10212818
    Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 19, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Fei Yu, Anwar A. Mohammed, Rui Niu
  • SENSOR SYSTEMS, DEVICES, AND METHODS FOR CONTINUOUS GLUCOSE MONITORING
    Publication number: 20190041345
    Abstract: Electrochemical impedance spectroscopy (EIS) may be used in conjunction with continuous glucose monitoring (CGM) to enable identification of valid and reliable sensor data, as well implementation of Smart Calibration algorithms.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 7, 2019
    Inventors: KEITH NOGUEIRA, TALY G. ENGEL, XIAOLONG LI, BRADLEY C. LIANG, RAJIV SHAH, JAEHO KIM, MIKE C. LIU, ANDY Y. TSAI, ANDREA VARSAVSKY, FEI YU
  • High-density and high-hardness graphene-based porous carbon material, method for making the same, and applications using the same
    Patent number: 10193156
    Abstract: A method for making graphene-based highly dense but porous carbon material with a high degree of hardness includes forming a sol by dispersing a graphene-based component in a solvent; preparing a graphene-based gel by reacting the sol in a reacting container at a temperature of about 20° C. to about 500° C. for about 0.1 hours to about 100 hours; and drying the gel at a temperature of about 0° C. to about 200° C. to obtain a material. A graphene-based porous carbon material and applications thereof are also disclosed.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 29, 2019
    Assignee: Graduate School at Shenzhen, Tsinghua University
    Inventors: Quan-Hong Yang, Ying Tao, Wei Lv, Bao-Hua Li, Cong-Hui You, Chen Zhang, Fei-Yu Kang
  • Methods for manufacturing graphene based material
    Patent number: 10193146
    Abstract: A method for manufacturing graphene-based material is disclosed. A graphene oxide dispersion includes graphene oxide dispersed in solvent. A hydrogen sulfide gas is introduced to the graphene oxide dispersion at a reacting temperature to achieve a graphene dispersion. The hydrogen sulfide reduces graphene oxide into graphene, and elemental sulfur produced from the hydrogen sulfide is deposited on surfaces of the graphene. The solvent and elemental sulfur are removed to achieve a graphene composite material.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 29, 2019
    Assignee: Graduate School at Shenzhen, Tsinghua University
    Inventors: Quan-Hong Yang, Chen Zhang, Wei Lv, Xiao-Yu Zheng, Wei Wei, Ying Tao, Bao-Hua Li, Fei-Yu Kang
  • Methods of manufacturing graphene based material
    Patent number: 10186707
    Abstract: A method for manufacturing graphene-based material is disclosed. A graphene oxide dispersion includes graphene oxide dispersed in solvent. A hydrogen sulfide gas is introduced to the graphene oxide dispersion at a reacting temperature to achieve a graphene dispersion. The hydrogen sulfide reduces graphene oxide into graphene, and elemental sulfur produced from the hydrogen sulfide is deposited on surfaces of the graphene. The solvent and elemental sulfur are removed to achieve a graphene composite material.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 22, 2019
    Assignee: Graduate School at Shenzhen, Tsinghua University
    Inventors: Quan-Hong Yang, Chen Zhang, Wei Lv, Xiao-Yu Zheng, Wei Wei, Ying Tao, Bao-Hua Li, Fei-Yu Kang
  • Semiconductor device and method for forming the same
    Patent number: 10181397
    Abstract: Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Heng Chen, Hui-Cheng Chang, Hong-Fa Luan, Xiong-Fei Yu, Chia-Wei Hsu
  • Edge Connector, Circuit Board, and Connector Component
    Publication number: 20180366847
    Abstract: An edge connector includes a first row of golden fingers and a second row of golden fingers. The first row of golden fingers is adjacent to a plugging end of the edge connector, and the second row of golden fingers is adjacent to the first row of golden fingers. In a plugging direction of the edge connector, each golden finger in the first row of golden fingers has a first end proximate to the plugging end and a second end opposite to the first end. A first end of a grounded golden finger in the first row of golden fingers is protruded from other golden fingers, and second ends of two or more than two golden fingers in the first row of golden fingers are not aligned with each other.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 20, 2018
    Inventors: Fei Yu, Shiping Cheng