Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT HEAT SPREADER INCLUDING SEALANT INTERFACE MATERIAL
    Publication number: 20210398871
    Abstract: A hybrid integrated heat spreader suitable for an integrated circuit (IC) die package. The hybrid integrated heat spreader includes a top sheet material and a sealant interface material located where the heat spreader is to contact an assembly substrate. The sealant interface material may offer greater adhesion to a sealant employed between the interface material and the package substrate. In some examples, the sealant interface material has a greater surface roughness and/or a different composition than a surface of the integrated heat spreader that is in close thermal contact with an IC die through a thermal interface material. With the sealant interface material improving adhesion, the sealant may have a higher bulk modulus, enabling the integrated heat spreader to impart greater stiffness to the IC die package assembly.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Sergio Antonio Chan Arguedas, Bamidele Daniel Falola
  • ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT ASSEMBLY CONNECTORS
    Publication number: 20210398922
    Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Feras Eid, Adel Elsherbini
  • ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT ASSEMBLY CONNECTOR SUPPORT STRUCTURES
    Publication number: 20210398715
    Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Johanna Swan, Georgios Dogiamis
  • PHYSICALLY UNCLONABLE FUNCTION CIRCUITRY OF A PACKAGE SUBSTRATE AND METHOD OF PROVIDING SAME
    Publication number: 20210398909
    Abstract: Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Feras Eid, Adel Elsherbini, David Johnston, Jyothi Bhaskarr Velamala, Rachael Parker
  • Hybrid filter architecture with integrated passives, acoustic wave resonators and hermetically sealed cavities between two resonator dies
    Patent number: 11206008
    Abstract: Embodiments of the invention include an acoustic wave resonator (AWR) module. In an embodiment, the AWR module may include a first AWR substrate and a second AWR substrate affixed to the first AWR substrate. In an embodiment, the first AWR substrate and the second AWR substrate define a hermetically sealed cavity. A first AWR device may be positioned in the cavity and formed on the first AWR substrate, and a second AWR device may be positioned in the cavity and formed on the second AWR substrate. In an embodiment, a center frequency of the first AWR device is different than a center frequency of the second AWR device. In additional embodiment of the invention, the AWR module may be integrated into a hybrid filter. The hybrid filter may include an AWR module and other RF passive devices embedded in a packaging substrate.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Telesphor Kamgaing, Feras Eid, Vijay K. Nair, Johanna M. Swan
  • MAGNETIC INDUCED HEATING FOR SOLDER INTERCONNECTS
    Publication number: 20210375820
    Abstract: Magnetic structures may be incorporated into integrated circuit assemblies, which will enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates. Such magnetic structures will eliminate exposure of the entire integrated circuit assembly to elevated temperatures for an extended period of time, which eliminates associated warpage and thermal degradation consequences from such exposure. Additionally, such magnetic structures will allow for re-workability of specific solder interconnects.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Georgios Dogiamis
  • STACKED DIE ARCHITECTURES WITH IMPROVED THERMAL MANAGEMENT
    Publication number: 20210375719
    Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventors: Feras Eid, Shrenik Kothari, Chandra M. Jha, Johanna M. Swan, Michael J. Baker, Shawna M. Liff, Thomas L. Sounart, Betsegaw K. Gebrehiwot, Shankar Devasenathipathy, Taylor Gaines, Digvijay Ashokkumar Raorane
  • Electrostatic discharge protection in integrated circuits
    Patent number: 11189580
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Dual-substrate waveguide filter
    Patent number: 11158917
    Abstract: Embodiments may relate to an assembly that includes a first package substrate with a first electromagnetic cavity. The assembly may further include a second package substrate with a second electromagnetic cavity that is adjacent to the first electromagnetic cavity. The first and second electromagnetic cavities may form a millimeter wave (mmWave) resonant cavity of a mmWave filter. Other embodiments may be described or claimed.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Telesphor Kamgaing, Georgios Dogiamis, Feras Eid, Johanna M. Swan
  • Microelectronic package electrostatic discharge (ESD) protection
    Patent number: 11147197
    Abstract: Embodiments may relate to a material to provide electrostatic discharge (ESD) protection in an electrical device. The material may include first and second electrically-conductive carbon allotropes. The material may further include an electrically-conductive polymer that is chemically bonded to the first and second electrically-conductive carbon allotropes such that an electrical signal may pass between the first and second electrically-conductive carbon allotropes. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
  • INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES
    Publication number: 20210296175
    Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS
    Publication number: 20210265732
    Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Inventors: Feras EID, Sasha N. OSTER, Telesphor KAMGAING, Georgios C. DOGIAMIS, Aleksandar ALEKSOV
  • HYBRID BACKSIDE THERMAL STRUCTURES FOR ENHANCED IC PACKAGES
    Publication number: 20210249375
    Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Applicant: INTEL CORPORATION
    Inventors: Feras Eid, Joe Walczyk, Weihua Tang, Akhilesh Rallabandi, Marco Aurelio Cartas Ayala
  • MICROELECTRONIC PACKAGE WITH MOLD-INTEGRATED COMPONENTS
    Publication number: 20210233856
    Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Inorganic dies with organic interconnect layers and related structures
    Patent number: 11062947
    Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • ELECTROSTATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITS USING POSITIVE TEMPERATURE COEFFICIENT MATERIAL
    Publication number: 20210202404
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • ELECTROSTATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITS USING MATERIALS WITH OPTICALLY CONTROLLED ELECTRICAL CONDUCTIVITY
    Publication number: 20210202403
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems
    Patent number: 11050155
    Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Feras Eid, Sasha N. Oster, Telesphor Kamgaing, Georgios C. Dogiamis, Aleksandar Aleksov
  • ELECTROSTATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITS
    Publication number: 20210193596
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: INTEL CORPORATION
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • DIODES FOR PACKAGE SUBSTRATE ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    Publication number: 20210193644
    Abstract: Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: December 21, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan