Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11283427
    Abstract: Hybrid filters and more particularly filters having acoustic wave resonators (AWRs) and lumped component (LC) resonators and packages therefor are described. In an example, a packaged filter includes a package substrate, the package substrate having a first side and a second side, the second side opposite the first side. A first acoustic wave resonator (AWR) device is coupled to the package substrate, the first AWR device comprising a resonator. A plurality of inductors is in the package substrate.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Feras Eid, Georgios C. Dogiamis, Vijay K. Nair, Johanna M. Swan
  • Patent number: 11264373
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Publication number: 20220042750
    Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11239155
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Patent number: 11233015
    Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Feras Eid
  • Patent number: 11234343
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11227859
    Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Shawna M. Liff
  • Patent number: 11227825
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
  • Patent number: 11226162
    Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11222856
    Abstract: Embodiments may relate to a package substrate that includes a signal line and a ground line. The package substrate may further include a switch communicatively coupled with the ground line. The switch may have an open position where the switch is communicatively decoupled with the signal line, and a closed position where the switch is communicatively coupled with the signal line. Other embodiments may be described or claimed.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Patent number: 11223524
    Abstract: Embodiments of the invention include a physiological sensor system. According to an embodiment the sensor system may include a package substrate, a plurality of sensors formed on the substrate, a second electrical component, and an encryption bank formed along a data transmission path between the plurality of sensors and the second electrical component. In an embodiment the encryption bank may include a plurality of portions that each have one or more switches integrated into the package substrate. In an embodiment each sensor transmits data to the second electrical component along different portions of the encryption bank. In some embodiments, the switches may be piezoelectrically actuated. In other embodiments the switches may be actuated by thermal expansion. Additional embodiments may include tri- or bi-stable mechanical switches.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Sasha N. Oster, Feras Eid, Georgios C. Dogiamis, Thomas L. Sounart, Johanna M. Swan
  • Patent number: 11221354
    Abstract: Embodiments of the invention include a resonant sensing system comprising driving circuitry to generate a drive signal during excitation time periods, a first switch coupled to the driving circuitry, and a sensing device coupled to the driving circuitry via the first switch during the excitation time periods. The sensing device includes beams to receive the drive signal during a first excitation time period that causes the beams to mechanically oscillate and generate a first induced electromotive force (emf) in response to the drive signal. The first switch decouples the sensing device and the driving circuitry during measurement time periods for measurement of the induced emf.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Sasha N. Oster, Feras Eid, Ian A. Young
  • Publication number: 20210410343
    Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
  • Publication number: 20210407903
    Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Henning Braunisch, Beomseok Choi, William J. Lambert, Stephen Morein, Ahmed Abou-Alfotouh, Johanna Swan
  • Publication number: 20210407884
    Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Xavier Brun, Paul Diglio, Joe Walczyk, Sergio Antonio Chan Arguedas
  • Publication number: 20210410331
    Abstract: System-level thermal solutions for integrated circuit (IC) die packages including a heat pipe contiguously integrated with base plate material at the hot interface or with heat sink material at the cold interface. Base plate material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of the heat pipe to form a base plate suitable for interfacing with an IC die package. The contiguous base plate material may offer low thermal resistance in the absence of any intervening joining material (e.g., solder or brazing filler). Solder or brazing filler may also be eliminated from between a heat sink and a heat pipe by depositing wick material directly upon the heat sink with an HTAM technique. The wick material may be then enclosed by attaching a preformed half-open tube.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Georgios Dogiamis
  • Publication number: 20210407888
    Abstract: A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Stephen Morein, Feras Eid, Georgios Dogiamis
  • Publication number: 20210407877
    Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Joe Walczyk, Paul Diglio
  • Publication number: 20210400856
    Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Adel Elsherbini, Feras Eid
  • Publication number: 20210398895
    Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Beomseok Choi, Henning Braunisch, William Lambert, Krishna Bharath, Johanna Swan