Patents by Inventor Fu Huang

Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240394510
    Abstract: An optimizing method of distributed training and a master computing apparatus are provided. In the method, a local model is trained by using one of multiple sample sets and a global parameter of a global model to generate a local parameter of the local model. One or more deviation parameters among the local parameter of multiple local models trained by the sample sets are determined. A distribution of the deviation parameter is far from a distribution of other local parameters, and the local parameter of the local models is used to update the global parameter of the global model. Accordingly, the prediction accuracy of the global model may be improved.
    Type: Application
    Filed: June 15, 2023
    Publication date: November 28, 2024
    Applicant: Wistron Corporation
    Inventor: Yuan Fu Huang
  • Publication number: 20240372776
    Abstract: A configuration method and a configuration unit are provided. The configuration method is for a configuration unit coupled to a cluster. The configuration method includes calculating a first node number at a first time instant, and selecting at least one first node corresponding to the first node number from at least one node of the cluster. The at least one first node is configured to run a plurality of network functions of a core network respectively. The coverage or processing capacity of the network of the cluster can be expanded or reduced by increasing or decreasing the total node number of the at least one node in the cluster. The dependence on data centers or telecommunication rooms can be reduced.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 7, 2024
    Applicant: Wistron Corporation
    Inventor: Yuan-Fu Huang
  • Publication number: 20240364640
    Abstract: A resource allocation method for a cloud environment includes steps performed by one or more servers. These steps include: obtaining an initial resource requirement, generating a first deployment parameter set according to the initial resource requirement by a first prediction model, configuring the cloud environment according to the first deployment parameter set by a resource allocator, obtaining and inputting the requests to a machine learning model in the cloud environment and generating a real resource requirement, generating a predicted resource requirement at least according to the real resource requirement by a second prediction model, when detecting that the cloud environment is in a busy state according to the predicted resource requirement by the resource allocator, generating a second deployment parameter set according to the real resource requirement by the first prediction model; and reconfiguring the cloud environment according to the second deployment parameter set by the resource allocator.
    Type: Application
    Filed: June 6, 2023
    Publication date: October 31, 2024
    Inventor: YUAN FU HUANG
  • Publication number: 20240350282
    Abstract: An expanded spinal fusion cage is provided and includes: an outer frame; a sliding block set with a middle sliding block located within the outer frame, and the middle sliding block is located between two outer sliding blocks; a screw rod penetrating through and combined with the outer frame, and the screw rod is screwed with the middle sliding block, so that the middle sliding block is moved in translation in the outer frame and simultaneously expands the two outer sliding blocks by rotating the screw rod; two curved surface elements located outside the outer frame and combined with the two outer sliding blocks respectively, each of the curved surface elements has a wing plate; and two vertebral arch screws penetrating through and combined with the two wing plates.
    Type: Application
    Filed: December 8, 2023
    Publication date: October 24, 2024
    Inventors: Chun-Li Lin, Shih-Chieh Shen, Shao-Fu Huang, Wei-Hsiang Sun
  • Patent number: 12114292
    Abstract: A resource adjustment method for a radio access network includes obtaining a plurality of radio access network training information at a first time point; predicting a radio access network usage condition of a second time point according to the plurality of radio access network training information; and pre-adjusting the radio access network resource allocation of the second time point according to the radio access network usage condition at a third time point, so as to allocate a plurality of user equipments to a plurality of radio units and adjust an arrangement of computing resources of a distributed unit and a central unit; wherein the first time point is earlier than the third time point, and the third time point is earlier than the second time point.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: October 8, 2024
    Assignee: Wistron Corporation
    Inventor: Yuan-Fu Huang
  • Patent number: 12061125
    Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 13, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Ming Hu, Chung-Kuang Chen, Chia-Ching Li, Chien-Fu Huang
  • Publication number: 20240252108
    Abstract: A detection method and an event detection system and an inference server are provided. The detection system includes a terminal device and an inference server. The terminal device generates first compressed data. The first compressed data is related to a sensing result of a physiological state or a motion state. The inference server decodes the first compressed data into reconstructed data via a decoder in an anomaly detection model, encodes the reconstructed data into second compressed data via an encoder, and determines an event of the physiological state or the motion state by an error between the first compressed data and the second compressed data. The anomaly detection model includes the decoder and the encoder. Accordingly, an amount of data can be reduced, and data protection is provided.
    Type: Application
    Filed: March 13, 2023
    Publication date: August 1, 2024
    Applicant: Wistron Corporation
    Inventor: Yuan Fu Huang
  • Publication number: 20240237549
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
  • Publication number: 20240237550
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
    Type: Application
    Filed: March 21, 2024
    Publication date: July 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
  • Patent number: 12019224
    Abstract: This document describes systems and techniques directed at an external wide-angle lens for imagers in electronic devices. An imager is disclosed that includes an image sensor and a lens stack, the lens stack including an external wide-angle lens, an internal lens, and four or more intermediate lenses. The imager has a first ratio of a projection at a vertex of the external wide-angle lens divided by a maximum focused dimension of the focal area being less than or equal to 0.15, a second ratio of a total length of the lens stack divided by the maximum focused dimension being less than or equal to 7.0, or a third ratio of a total transmission length of the imager divided by an entrance pupil diameter of the external wide-angle lens being between 1.2 and 2.6.
    Type: Grant
    Filed: September 25, 2023
    Date of Patent: June 25, 2024
    Assignee: Google LLC
    Inventors: Shan Fu Huang, Chen Cheng Lee, Tsung-Dar Cheng, Calvin Kyaw Wong
  • Patent number: 12015564
    Abstract: A network management method and a network entity are provided. In the method, a detection result is obtained. One of multiple network slices is switched to another according to the detection result. The detection result is a result of detecting an image. Each network slice provides a network resource. The image is accessed through the network resource. Accordingly, a network setting parameter could be dynamically adjusted to save energy.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: June 18, 2024
    Assignee: Wistron Corporation
    Inventor: Yuan Fu Huang
  • Publication number: 20240186447
    Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 6, 2024
    Inventors: Chien-Fu HUANG, Chih-Chiang LU, Chun-Yu LIN, Hsin-Chih CHIU
  • Patent number: 11998894
    Abstract: A composite solid base catalyst, a manufacturing method thereof and a manufacturing method of glycidol are provided. The composite solid base catalyst includes an aluminum carrier and a plurality of calcium particles. The plurality of calcium particles are supported by the aluminum carrier. Beta basic sites of the composite solid base catalyst are 0.58 mmol/g-3.89 mmol/g.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: June 4, 2024
    Assignees: NATIONAL TSING HUA UNIVERSITY, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., LTD., DAIREN CHEMICAL CORP.
    Inventors: De-Hao Tsai, Yung-Tin Pan, Che-Ming Yang, Ching-Yuan Chang, Ding-Huei Tsai, Chien-Fu Huang, Yi-Ta Tsai
  • Publication number: 20240176191
    Abstract: An electronic device includes a first substrate, a first protrusion, a second protrusion and a plurality of third protrusions. The first substrate includes an edge, a first region, and a second region. The first substrate includes a surface. The first protrusion is in the first region. A maximum distance from the surface to a top surface of the first protrusion is defined as a first distance. The second protrusion is in the second region. A maximum distance from the surface to a top surface of the second protrusion is defined as a second distance. The first protrusion is disposed between two of the third protrusions. A maximum distance from the surface to a top surface of the third protrusion is defined as a third distance. The first distance is different from the second distance, and the third distance is less than the first distance.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 30, 2024
    Inventors: Tang-Chin HUNG, Zhi-Fu HUANG
  • Patent number: 11993676
    Abstract: A non-fullerene acceptor polymer includes a structure represented by formula (I). Formula (I) is defined as in the specification. The non-fullerene acceptor polymer has an electron donating unit and an electron attracting end group. The non-fullerene acceptor polymer uses phenyl or its derivatives as the linker to form the polymer.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: May 28, 2024
    Assignee: National Tsing Hua University
    Inventors: Ho-Hsiu Chou, Mohamed Hammad Elsayed, Chih-Wei Juan, Tse-Fu Huang
  • Publication number: 20240153900
    Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: SHENG-FU HUANG, SHING-YIH SHIH
  • Publication number: 20240153902
    Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.
    Type: Application
    Filed: September 13, 2023
    Publication date: May 9, 2024
    Inventors: SHENG-FU HUANG, SHING-YIH SHIH
  • Publication number: 20240146665
    Abstract: A network management method and a network entity are provided. In the method, a detection result is obtained. One of multiple network slices is switched to another according to the detection result. The detection result is a result of detecting an image. Each network slice provides a network resource. The image is accessed through the network resource. Accordingly, a network setting parameter could be dynamically adjusted to save energy.
    Type: Application
    Filed: February 10, 2023
    Publication date: May 2, 2024
    Applicant: Wistron Corporation
    Inventor: Yuan Fu Huang
  • Patent number: 11968906
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: April 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
  • Publication number: 20240118721
    Abstract: A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The voltage control method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; and controlling the driving circuit by a first regulator circuit to adjust the output voltage in response to a current change caused by the feedback voltage.
    Type: Application
    Filed: November 23, 2022
    Publication date: April 11, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Huang, Bing-Wei Yi