Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.

Abstract: The disclosure provides an electromagnetic wave adjusting device, including a first substrate, a first conductive element, a second substrate, a second conductive element, and a dielectric layer. The first conductive element is disposed on the first substrate. The second substrate is opposite to the first substrate. The second conductive element is disposed on the second substrate and faces the first substrate, in which the first conductive element has an overlapping region which overlaps the second conductive element. The dielectric layer is disposed between the first substrate and the second substrate. The electromagnetic wave adjusting device includes a working region and a non-working region. The working region includes the overlapping region. The non-working region is disposed outside the working region. A first region in the non-working region and a second region in the working region have the same film-layer stack structure.

Abstract: The present disclosure provides a semiconductor device, including a buffer layer, a first sub-chip and a second sub-chip, and a connecting element. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer in a top-down approach. The first diffusion layer and the buffer layer are first-type epitaxial layers, and the second diffusion layer is a second-type epitaxial layer. The connecting element is configured to couple the second diffusion layer of the first sub-chip and the first diffusion layer of the second sub-chip.

Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.

Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

Abstract: The present disclosure provides a light emitting diode component, including a body and a plurality of P-N diode structures. The P-N diode structures are coupled in series and integrated on the body. The P-N diode structures include a plurality of p-type doping layers and a plurality of n-type doping layers. The p-type doping layer of a first P-N diode structure in the P-N diode structures is electrically coupled to the n-type doping layer of a second P-N diode structure in the P-N diode structures.

Abstract: A control method of a flyback power converter includes a voltage detection pin detecting conduction time of a power switch of a primary side of the flyback power converter, a feedback pin detecting conduction time of a synchronous switch of a secondary side of the flyback power converter, the feedback pin detecting a number of inductor capacitor resonant valleys when the flyback power converter operates in a discontinuous conduction mode, and a high voltage detection pin detecting an input voltage inputted in the flyback power converter; and a controller applied to the flyback power converter making the flyback power converter operate in a quasi-resonant mode when the number of the inductor capacitor resonant valleys is greater than a predetermined number, an operational frequency of the flyback power converter is less than a predetermined frequency, and the input voltage is less than a predetermined voltage.

Abstract: A method for generating a random number, applied in a random number generator coupled to a flash memory is disclosed. the method comprises: selecting a plurality of cells from the flash memory; initializing the selecting cells of the flash memory; programming the selecting cells to obtain a plurality of first potential values of the selecting cells; re-initializing the selecting cells of the flash memory; re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; and processing the first potential values and the second potential values according to a predetermined algorithm to generating the random number.

Abstract: A method for detecting whether glucose metabolism is abnormal comprises: detecting GPx2 gene expression, GPx2 protein expression or the activity of GPx2 protein in a test body, and making comparisons with GPx2 expression amount of a normal individual, when the GPx2 expression of the individual is significantly lower than that of the normal individual, indicating that the carbohydrate metabolism of the individual is in an abnormal state. Applications of GPx2 in the preparation of a medical composition for the treatment and prevention of type II diabetes.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Abstract: A reliability evaluation method for a multi-state distributed network system is provided. The network system includes a network topology of Internet of Things (IoT) devices, edge servers, cloud servers, transmission nodes and transmission arcs. The capacity of the transmission arc is regarded as a random multi-state. The data generated by the IoT devices are transmitted to the edge servers. After processing and compression by the edge servers, the data are transmitted to the cloud servers for calculation. System reliability is defined as the probability that a specific amount of data can be successfully transferred from the IoT devices to the cloud servers. Algorithms are used to calculate the transmission mechanism between the IoT devices, the edge servers, and the cloud servers, evaluate the quality and reliability of multi-state distributed network systems, and further serve as an indicator of system management. Sensitivity analysis is also used to improve quality.

Abstract: A device for capturing particles includes a gas-guiding unit, a gas-guiding unit and a mist-elimination unit. The gas-guiding unit has opposing first and second ends. The mist-elimination unit is disposed at the second end. The liquid-circulation unit, disposed under the mist-elimination unit by surrounding the gas-guiding unit, includes through holes below the gas-guiding unit by a gap. A gas containing particles enters the channel via the first end and then the mist-elimination unit via the second end. While the gas flows into the channel, the liquid in the liquid-circulation unit is inhaled into the channel via the gap to form droplets containing particles. After the droplets are captured by the mist-elimination unit, the liquid formed at the mist-elimination unit flows down into the liquid-circulation unit to reform the liquid to be further inhaled back to the channel of the gas-guiding unit via the gap.

Abstract: A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer.

Abstract: A connector structure is provided. The connector structure includes an insulated housing and at least one terminal assembly. The terminal assembly includes an insulated shelter and at least one pins. The pins are connected to and penetrated through the insulated shelter. The pin includes a pin body and at least two protrusive portions. Each protrusive portion is connected to the pin body, and in a length direction of the pin body, the protrusive portions respectively extend corresponding contact portions. The contact portion is in contact with a corresponding signal pad of a circuit board, and the contact portions are at different positions of the signal pad. In additional, a terminal components of connector is also provided.

Abstract: A connector structure is provided. The connector structure includes an insulated housing and at least one terminal assembly. The terminal assembly includes an insulated shelter and at least one pins. The pins are connected to and penetrated through the insulated shelter. The pin includes a pin body and at least two protrusive portions. Each protrusive portion is connected to the pin body, and in a length direction of the pin body, the protrusive portions respectively extend corresponding contact portions. The contact portion is in contact with a corresponding signal pad of a circuit board, and the contact portions are at different positions of the signal pad. In additional, a terminal components of connector is also provided.

Abstract: A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.

Abstract: A connector structure includes an insulated housing, at least one terminal assembly and at least one conductive assembly. The terminal assembly is disposed in the insulated housing. The conductive assembly is disposed at one side of the terminal assembly by crossing over the terminal assembly. The conductive assembly includes at least one metal piece and at least one polymer included conductive component. The polymer included conductive component is used to electrically connect the at least one metal pieces. The metal piece includes at least one spring finger contact, and the spring finger contact is electrically connected to the ground terminal in the terminal assembly. In additional, a terminal assembly structures of connector is also provided.

Abstract: A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer.