Patents by Inventor Fu Huang

Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220148915
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 12, 2022
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Sheng-Fu Huang
  • Publication number: 20220124155
    Abstract: A reliability evaluation method for a multi-state distributed network system is provided. The network system includes a network topology of Internet of Things (IoT) devices, edge servers, cloud servers, transmission nodes and transmission arcs. The capacity of the transmission arc is regarded as a random multi-state. The data generated by the IoT devices are transmitted to the edge servers. After processing and compression by the edge servers, the data are transmitted to the cloud servers for calculation. System reliability is defined as the probability that a specific amount of data can be successfully transferred from the IoT devices to the cloud servers. Algorithms are used to calculate the transmission mechanism between the IoT devices, the edge servers, and the cloud servers, evaluate the quality and reliability of multi-state distributed network systems, and further serve as an indicator of system management. Sensitivity analysis is also used to improve quality.
    Type: Application
    Filed: May 17, 2021
    Publication date: April 21, 2022
    Inventors: Yi-Kuei LIN, Ding-Hsiang HUANG, Cheng-Fu HUANG
  • Patent number: 11309648
    Abstract: A connector structure with improved terminal coplanarity includes a housing and terminal assemblies. The housing has sockets and a coplanar track. The coplanar track is defined by two inner flanges of the housing. The two flanges extend longitudinally and parallel to each other. Each terminal assembly includes a connector body, terminals and a guider. The connector body is disposed inside the housing by the sockets. The terminals are disposed by penetrating through the connector body. The guider is disposed close to soldering ends of the terminals. The soldering end of each terminal protrudes out of the guider. The guider has two opposite grooves. Each groove is engaged with the corresponding flange. The coplanar track has a coplanar datum surface. Soldering portions of the soldering ends of the terminals protruding out of the guider are separated from the coplanar datum surface by the same distance.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 19, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Tien-Fu Huang
  • Patent number: 11294845
    Abstract: An information handling system couples a solid state drive assembly having plural solid state drives to a motherboard with a single M.2 connector coupled to the motherboard by interfacing the plural solid state drives with an adapter circuit board having an M.2 interface defined at one end to insert into the motherboard connector and having plural M.2 connectors to interface with the plural solid state drives in a desired configuration, such as a stacked vertical configuration that more efficiently uses motherboard footprint to include persistent memory.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 5, 2022
    Assignee: Dell Products L.P.
    Inventors: Yao-Fu Huang, Chun Min He, Yi-Ning Shen
  • Patent number: 11289370
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Sheng-Fu Huang
  • Patent number: 11282581
    Abstract: A memory device has a plurality of blocks of memory cells and a plurality of bit lines, each block including a group of word lines, and a set of NAND strings. Each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block selected, and a respective sub-block string select line. Control circuits are configured to execute a program operation including applying word line voltages and string select line voltages at a precharge level to precharge the set of NAND strings in the selected block, then lowering the gate voltages on all the sub-block string select lines of the block, and then lowering the word line voltages on the group of word lines. Thereafter, the program of cells in a selected sub-block is executed.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 22, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Sung Chen, Chien-Fu Huang
  • Patent number: 11239243
    Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 1, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Patent number: 11228133
    Abstract: A high speed connector includes an insulated shelter for accommodating at least one main body. The main body includes at least one terminal group integrated with the main body by having two opposing sides thereof to extend out of the main body, in which the two opposing sides are defined as a contact portion and a welding portion, respectively. The terminal group further includes a plurality of terminals. The insulated plastic element has a slot for enclosing up terminal group, and a height of a section in the slot is larger than a thickness of the plurality of terminals, so that at least one gap can be formed in the slot. By having the gap, dielectric coefficients and electromagnetic properties around the terminals can be adjusted to reduce the crosstalk effects upon the signal terminals. In addition, an insulated plastic element is also provided.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: January 18, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Tien-Fu Huang
  • Publication number: 20220005758
    Abstract: A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
  • Patent number: 11217525
    Abstract: A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Sheng-Fu Huang, Shing-Yih Shih
  • Publication number: 20210408226
    Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventors: Chung-Kuang CHEN, Chia-Ching LI, Chien-Fu HUANG, Chia-Ming HU
  • Patent number: 11202854
    Abstract: Disclosed herein are disintegrin variants, and methods for suppressing or inhibiting platelet aggregation in a subject in need thereof. The method includes administering to the subject in need thereof an effective amount of the present disintegrin variant to alleviate or ameliorate symptoms associated with diseases, disorders, and/or conditions resulted from platelet aggregation. According to preferred embodiments, the present disintegrin variant is applied as a coating on an implantable device, such as a stent or a catheter.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 21, 2021
    Assignees: NATIONAL TAIWAN UNIVERSITY, NATIONAL CHENG KUNG UNIVERSITY, DCB-USA LLC
    Inventors: Tur-Fu Huang, Yu-Ju Kuo, Woei-Jer Chuang
  • Publication number: 20210367098
    Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Chien-Fu HUANG, Chih-Chiang LU, Chun-Yu LIN, Hsin-Chih CHIU
  • Publication number: 20210354089
    Abstract: The invention relates to the technical field of membrane separation, in particular to and discloses a preparation method of a high-performance MABR hollow fiber composite membrane, which comprises the following steps: 1) pretreating a supporting membrane, which includes: soaking the supporting membrane in ethanol, then soaking the supporting membrane in pure water, and then removing residual water; 2) preparing a coating solution, which includes: mixing raw silicone rubber and a reinforcing material with a continuous stirring, adding a crosslinking agent and a catalyst and stirring well, adding a solvent to dilute to a required concentration, and perform a vacuum defoaming; 3) coating the pretreated supporting membrane, which includes: coating and pulling; and 4) performing a curing, which includes: placing the membrane in an oven for curing.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 18, 2021
    Applicant: Zhejiang Changxing Creflux Membrane Technology Co., Ltd.
    Inventors: Hao Wu, Hongmei Shen, Fu Huang, Zhipeng Xu, Shantian Xu, Limin Cao, Jinfeng Bao
  • Publication number: 20210356791
    Abstract: An electronic modulating device is provided. The electronic modulating device includes a first substrate. The first substrate includes a first portion and a second portion. The electronic modulating device also includes a second substrate disposed opposite to the first substrate. The electronic modulating device further includes at least one working device disposed between the first substrate and the second substrate, wherein the working device overlaps the first portion and does not overlap the second portion. In addition, the electronic modulating device includes a first adjustment unit disposed between the first portion of the first substrate and the second substrate. The first adjustment unit has a first elastic coefficient. The electronic modulating device also includes second adjustment unit disposed between the second portion of the first substrate and the second substrate. The second adjustment unit has a second elastic coefficient that is greater than the first elastic coefficient.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Tang-Chin HUNG, Zhi-Fu HUANG
  • Publication number: 20210351347
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20210343931
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
    Type: Application
    Filed: May 25, 2020
    Publication date: November 4, 2021
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
  • Patent number: 11165019
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20210326291
    Abstract: An information handling system couples a solid state drive assembly having plural solid state drives to a motherboard with a single M.2 connector coupled to the motherboard by interfacing the plural solid state drives with an adapter circuit board having an M.2 interface defined at one end to insert into the motherboard connector and having plural M.2 connectors to interface with the plural solid state drives in a desired configuration, such as a stacked vertical configuration that more efficiently uses motherboard footprint to include persistent memory.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 21, 2021
    Applicant: Dell Products L.P.
    Inventors: Yao-Fu Huang, Chun Min He, Yi-Ning Shen
  • Publication number: 20210325261
    Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.
    Type: Application
    Filed: September 3, 2020
    Publication date: October 21, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Ming HU, Chung-Kuang CHEN, Chia-Ching LI, Chien-Fu HUANG