Patents by Inventor Fu Lin

Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Condition responsive circuit protection apparatus which can enter an energy saving mode
    Patent number: 9112352
    Abstract: A circuit protection apparatus is disclosed. A peripheral interface includes a first power node and a second power node. The circuit protection apparatus includes an auxiliary power supply circuit, a power converter, a first switch, a second switch, a power switch circuit, a warning circuit, and a controller. When a load is plugged to the peripheral interface, the first switch turns on, and the controller is enabled and outputs a control signal, so as to drive the power converter to output power. When the current between input terminal and output terminal of the power switch circuit is larger than a predetermined current, the controller receives the error flag logical voltage outputted by the power switch circuit, cuts off the current between input terminal and output terminal of the power switch circuit, and stops the operations of the power converter.
    Type: Grant
    Filed: February 2, 2013
    Date of Patent: August 18, 2015
    Inventors: Shu-Ling Chen, Chun-Fu Lin
  • Process for producing conjugated diene rubber and composite of the same rubber
    Patent number: 9109071
    Abstract: A process for producing conjugated diene rubber and its composite includes polymerizing a conjugated diene or a conjugated diene and a vinyl aromatic hydrocarbon in a hydrocarbon solution by anionic polymerization to obtain conjugated diene rubber containing alkali metal in the polymer chain end reacting with at least one organic silane compound to become a modified conjugated diene rubber. After or during the modified conjugated diene rubber contacting with large amount of water, solvent and water content are removed from the modified conjugated diene by applicable hot sources, wherein coupling ratio of modified conjugated diene rubber is less than 40%, coupling ratio of modified conjugated diene rubber after contact with water is at least 50% The conjugated diene rubber and composite exhibit storage stability.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: August 18, 2015
    Inventors: Chi-Chen Hsieh, Fu Lin, Chi-Ta Tsai
  • Apparatus and method for driving light emitting diode
    Patent number: 9099044
    Abstract: A driving apparatus for driving at least one first light emitting diode unit and a second light emitting diode unit includes a data transmitting unit and a driving unit. The data transmitting unit is used for receiving and storing driving data. The driving data includes first data corresponding to a first driving signal and second data corresponding to a second driving signal. The driving unit divides the first driving signal into a plurality of first sub-driving signals and the second driving signal into a plurality of second sub-driving signals, and then alternately outputs the first sub-driving signals and the second sub-driving signals to alternately drive the first light emitting diode unit and the second light emitting diode unit.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: August 4, 2015
    Assignee: MY-SEMI Inc.
    Inventors: Chun-Ting Kuo, Chun-Fu Lin, Cheng-Han Hsieh
  • Copper bump structures having sidewall protection layers
    Patent number: 9093314
    Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Po-Hao Tsai, Yan-Fu Lin, Cheng-Lin Huang, Fang Wen Tsai, Wen-Chih Chiou
  • METHOD OF FORMING INTER-LEVEL DIELECTRIC LAYER
    Publication number: 20150206803
    Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.
    Type: Application
    Filed: January 19, 2014
    Publication date: July 23, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Tzu-Chin Wu, Jei-Ming Chen, Yu-Ren Wang, Chun-Yuan Wu, Chin-Fu Lin
  • Manufacturing process of gate stack structure with etch stop layer
    Patent number: 9087782
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 21, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Transistor and semiconductor structure
    Patent number: 9076784
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 7, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • DISPLAY DEVICE WITH COLOR CONVERSION LAYER FOR FULL-COLOR DISPLAY
    Publication number: 20150185381
    Abstract: A display device with a color conversion layer providing predetermined colors for full-color display. The color conversion layer includes a plurality of color conversion units. Each color conversion unit includes a quantum dot film. The color conversion unit is configured to receive light beams and converts the light beams to primary colors to emit. Each color conversion unit defines a plurality of areas, and each primary color corresponds to one of the areas of the color conversion unit.
    Type: Application
    Filed: December 24, 2014
    Publication date: July 2, 2015
    Inventors: I-Wei WU, Yung-Fu LIN, Chang-Ting LIN, Shih-Pin TSENG, Pen-Chu LIN
  • EVALUATION METHOD FOR CALIBRATION OF PROCESSING EQUIPMENT
    Publication number: 20150169422
    Abstract: The present invention provides an evaluation method for calibration of a processing equipment. According to the present invention, prior to processing a device, a test member including the same thickness and material with the device is manufactured. Then, the processing equipment is used to process the device, the test member and form a micro-processing structure in the test member. Next, the status of the micro-processing structure in the test member is inspected for evaluating if the processing equipment should be calibrated. In this way, the size and shape accuracy of the formation micro-processing structures using the monitored processing equipment can be reasonably guaranteed.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: FU-CHUAN HSU, YU-FU LIN, TSUNG-PIN HUNG, YU-TING LYU, ZHENG-HAN HUNG
  • Electronic device and method for image stabilization
    Patent number: 9055222
    Abstract: An electronic device and methods for image stabilization for use in an electronic device are provided. The method includes the steps of: receiving a plurality of motion data, at least a portion of the plurality of motion data corresponding to a first image frame, determining a motion value corresponding to the first image frame according to the portion of motion data, determining a display offset between the first image frame to a reference image frame according to the motion value and providing a portion of the first image frame for display according to the display offset. The reference image frame is displayed prior to the first image frame and is stored in a storage unit.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: June 9, 2015
    Assignee: HTC CORPORATION
    Inventors: Ching-Fu Lin, Pol-Lin Tai, Cheng-Hsien Lin, Jing-Lung Wu, Hsin-Ti Chueh
  • Methods for image processing of face regions and electronic devices using the same
    Patent number: 9049355
    Abstract: An embodiment of the invention discloses a face-slimming method applied to a series of images captured by an electronic device. The process begins to receive a current image from the series of captured images and detects at least one face landmark corresponding to a face region of the current image. The face landmark of the current image is compared with a reference landmark and a distortion mask is adjusted accordingly. And then, a size of the face region within the current image is then adjusted according to the distortion mask, where the distortion mask corresponds to positions of the face landmark.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 2, 2015
    Assignee: HTC CORPORATION
    Inventors: Ching-Fu Lin, Pol-Lin Tai, Huai-Che Lee, Jing-Lung Wu, Hsin-Ti Chueh
  • Semiconductor structure having a metal gate with side wall spacers
    Patent number: 9048254
    Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: June 2, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
  • BUCKLE ASSEMBLY
    Publication number: 20150135492
    Abstract: A buckle assembly comprises female and male buckle plates. The female buckle plate is formed with an insertion slot defined by a slot-defining wall having first and second wall faces, and has first and second corners. The first and second corners oppose each other, and are different in height with respect to a reference plane. The male buckle plate has a bent end portion that has upper and lower segments and a middle segment cooperating with the upper and lower segments to define upper and lower corners. The bent end portion is pivotable to the first corner by abutting the upper corner against the first corner, such that the bent end portion is rotatable relative to the first corner.
    Type: Application
    Filed: March 5, 2014
    Publication date: May 21, 2015
    Applicant: Plus Meditech Co., Ltd.
    Inventors: Yueh-Hua CHIANG, Fu-Lin CHUANG
  • HINGE FOR AN ORTHOPEDIC BRACE
    Publication number: 20150141888
    Abstract: A hinge for an orthopedic brace includes: a pivot shaft; a lower leg plate pivoted to the pivot shaft; an upper leg plate; a catch plate having a toothed peripheral edge; and two position adjusting units, each of which includes a rotatable limiting seat, a limiting pin, and a slider body. The rotatable limiting seat defines a housing chamber therein, and is formed with a wall slot. The slider body is slidably disposed in the housing chamber. The limiting pin extends from the slider body through the wall slot for engaging and disengaging the toothed peripheral edge. The catch plate is formed with a guiding groove. The rotatable limiting seat has a tongue protruding into the guiding groove.
    Type: Application
    Filed: March 12, 2014
    Publication date: May 21, 2015
    Applicant: Plus Meditech Co., Ltd.
    Inventors: Yueh-Hua CHIANG, Fu-Lin CHUANG
  • Substrate with integrated passive devices and method of manufacturing the same
    Patent number: 9035457
    Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu Lin, Ming-Tse Lin, Yung-Chang Lin
  • METHOD FOR FORMING A FINFET STRUCTURE
    Publication number: 20150132966
    Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 14, 2015
    Inventors: Hung-Lin Shih, Jei-Ming Chen, Chih-Chien Liu, Chin-Fu Lin, Kuan-Hsien Li
  • Manufacturing method for semiconductor device having metal gate
    Patent number: 9024393
    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
  • Looped-cord system for window coverings
    Patent number: 9016347
    Abstract: A looped-cord system includes a beaded cord having a set of beads connected in series to form a loop with a space between each pair of adjacent beads. In one embodiment a stop sized to fit within the space between a pair of adjacent beads is attached to a housing. A resilient finger located opposite the stop pushes a portion of the beaded cord adjacent to and not engaging the sprocket against the stop so the stop is within a space between a pair of adjacent beads, thereby preventing movement of the cord loop. Applying tension to the cord loop overcomes the resilient finger and moves the cord away from the stop enabling movement of the cord loop. In another embodiment a key engages the sprocket preventing the sprocket from turning until tension is applied to the cord loop by proper installation of the tensioner on the cord loop.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 28, 2015
    Assignee: Whole Space Industries Ltd.
    Inventor: Tzong-Fu Lin
  • Method of fabricating semiconductor device
    Patent number: 9018087
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu
  • Semiconductor device having a metal gate and fabricating method thereof
    Patent number: 9018086
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen