Abstract: A trigger structure for switching one shoot mode or repeat shoot mode includes a trigger member and a switching member. The trigger member has a recess defined laterally. Two protrusions are defined in the inner wall of the recess. The switching member has an adjusting member and a trigger plate. Under this arrangement, when the adjusting member is pressed into the recess, the trigger plate is at one position to allow the trigger to shoot in a repeat shoot mode; when the adjusting member is turned to abut against the two protrusions, the trigger plate is at another position to allow the trigger to shoot in a one shoot mode.

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract: The invention provides a boundary radiation prevention structure, comprising: a metal portion, and a guide portion. The metal portion has an incident plane adapted to block an incident electromagnetic wave, wherein the incident electromagnetic wave induces an induced current on the incident plane. The guide portion is located on one border of the incident plane and has a curved surface electrically connected to the metal portion for the induced current to pass through, wherein the curved surface is covered by an absorption layer for absorbing the incident electromagnetic wave and a boundary radiation generated from the induced current radiation.

Abstract: The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

Abstract: A color filter array includes a substrate, a light shielding layer, and color filter patterns. The light shielding layer is on the substrate and has openings exposing a surface of the substrate. Besides, the light shielding layer has a height H. The color filter patterns are located in the openings of the light shielding layer. Each color filter pattern has the maximum film thickness Lc and the minimum film thickness Ls, and the difference between the maximum film thickness Lc and the minimum film thickness Ls is ?L. The maximum film thickness Lc of each color filter pattern satisfies (m×H)<Lc<(n×H), wherein m comprises about 0.83, n comprises about 0.91, the height H of the light shielding layer satisfies a<H<b, wherein a comprises about 1.6 um and b comprises 2.22 um, and the difference ?L is less than about 0.39 um.

Abstract: A display device and color filter substrate thereof are provided. The color filter substrate includes a substrate and a green color filter disposed on the substrate. A concentration of halogen in the green color filter is less than 10 ppm. The green color filter has a transmittance spectrum G(?), and CMF_Z(?) is the color matching function defined by International Commission on Illumination (CIE). A peak intensity between 380 nm and 780 nm of G(?)×CMF_Z(?) is in a range between 0.33 and 0.4.

Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.

Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

Abstract: A wafer edge trimming method comprises steps as follows: Firstly, an etch-resistant layer is formed on a surface of a wafer. A wet treatment process is then performed to remove a portion of the etch-resistant layer, so as to expose a portion of the surface adjacent to an edge of the wafer. Subsequently, an etching process is performed to remove a portion of the wafer that is not covered by the remained etch-resistant layer.

Abstract: A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor.

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

Abstract: The present invention provides a dual chip signal conversion device, comprising: a carrier, one side surface thereof being provided with at least a first contact and a second contact while the other side surface thereof being provided with at least a third contact and a fourth contact; a first chip disposed at one side surface of the carrier and electrically connected to the second and fourth contacts; a second chip disposed at one side surface of the carrier and electrically connected to the first chip; and an antenna disposed within the carrier and electrically connected to the second chip.

Abstract: A window covering includes a plurality of cord shrouds for enclosing or covering lift cords. Each of the cord shrouds may be continuously attached to the window covering material via a continuous attachment mechanism that includes one or more columns of stitching, beads of adhesive or welding. The cord shrouds may prevent the lift cords from being pulled away from the window covering material to form loops that could pose a danger to a young child. Embodiments of the window covering may be configured as top down bottom up shades or other types of shades. The window covering material may be composed of any of a number of different materials. For example, the window covering material could include pleated material, or could be comprised of a sheet of material consisting of woven wood, interconnected fabric segments, non woven fabric or woven fabric.

Abstract: An embodiment of the invention discloses a face-slimming method applied to a series of images captured by an electronic device. The process begins to receive a current image from the series of captured images and detects at least one face landmark corresponding to a face region of the current image. The face landmark of the current image is compared with a reference landmark and a distortion mask is adjusted accordingly. And then, a size of the face region within the current image is then adjusted according to the distortion mask, where the distortion mask corresponds to positions of the face landmark.

Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.