Patents by Inventor Fu Lin

Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8523457
    Abstract: An optical-fiber connector includes an insulative main body having a pair of optical components extending forwardly therefrom. Each optical component defines at least one lens and a guiding post located at outside of the lens. Each guiding post defines a through hole extend through the guiding post and the main body in a front-to-back direction and fulfilled with the air for transmitting a test light. The test light from the through hole of the guiding post acts as an accurate measuring reference of the true position between the lens and the fiber because of having no displacement of the light path through a through hole.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: September 3, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Hsu-Chih Liu, Yen-Chih Chang, Chun-Fu Lin
  • Patent number: 8518634
    Abstract: A method of making an integrated circuit is provided. The method includes providing a substrate having a photosensitive layer. The photosensitive layer is exposed to a radiation beam. The exposed photosensitive layer is developed in a first chamber. In the first chamber, a cleaning process is performed on the developed photosensitive layer. The cleaning process includes using a rinse solution including at least one of ozone, hydrogen peroxide, and oxalic acid.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Yu-Fu Lin, Shao-Yen Ku, Chi-Ming Yang, Chin-Hsiang Lin
  • Publication number: 20130214336
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, Jing-Gang Li, Min-Hsien Chen, Jian-Hong Su
  • Patent number: 8513519
    Abstract: This invention relates to a method for making an electrolyte composition of a dye-sensitized solar cell comprising utilizing exfoliated clay nanoplatelets and the method for rapidly encapsulating cations. The electrolyte composition mainly includes exfoliated clay nanoplatelets, an ionic liquid and iodine. The method for rapidly encapsulating cation comprises adding the exfoliated clay nanoplatelets into a cationic solution, wherein the exfoliated clay nanoplatelets encapsulates cations and recovers into a layered structure such that phase separation of the solution occurs; and filtrating the solution to separate the clay nanoplatelets encapsulating the cations. The exfoliated clay nanoplatelets have a unique property of encapsulation for the cations, is suitable for use in an electrolyte composition for dye-sensitized solar cells, cationic drug encapsulation and environmental protection.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: August 20, 2013
    Assignee: National Taiwan University
    Inventors: King-Fu Lin, Chia-Hsin Lee, Keng-Jen Lin, Ken-Yen Liu
  • Patent number: 8511363
    Abstract: A window covering includes a roller attached to a mounting device and an actuation device attached to the roller to rotate the roller in at least one of a first direction and a second direction. A front member is attached to the mounting device. A second member is attached to the roller. A plurality of ballast members are attached to the front member. Each ballast member has a portion that extends to the second member to engage the second member to cause the front member to form substantially parallel folds when the second member is wound about the roller to retract the front member to a retracted position. Preferably, the folds are similar to or exactly like the transverse folds in shade material that are formed when a conventional Roman shade is raised.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 20, 2013
    Assignee: Whole Space Industries Ltd.
    Inventor: Tzong-Fu Lin
  • Publication number: 20130207122
    Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Patent number: 8502713
    Abstract: A method for correcting a voltage offset influence of a pipelined analog to digital converter is disclosed, in which the method generates a first stage code and a first output voltage according to a first input voltage, generates a second stage code according to the first output voltage, generates a check code according to the first output voltage, determines a first correction code by referring to the first stage code and the check code, and corrects the first stage code with the first correction code when the first stage code is different from the first correction code.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Himax Technologies Limited
    Inventor: Jin-Fu Lin
  • Patent number: 8500488
    Abstract: An electrical connector includes an insulative housing (1), a plurality of contact terminals (2) arranged in an X direction and a metallic shell (3) covering an outside of the insulative housing thereby forming a mating space (151) with a mating opening (152). The metallic shell (3) has a main plate (30) and a plurality of T-shaped retaining tabs (31) extending into mating space from the main plate and engaging with an inner surface (111) of the side wall (11).
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: August 6, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Hsiu-Yuan Hsu, Chun-Fu Lin
  • Publication number: 20130193585
    Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Inventors: Chin-Fu Lin, Chun-Yuan Wu, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien
  • Patent number: 8497198
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Patent number: 8497584
    Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
  • Patent number: 8493259
    Abstract: A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Shi Jordan Lai, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng, Chih-Cheng Lu, Manoj M. Mhala, Yung-Fu Lin
  • Patent number: 8493260
    Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 23, 2013
    Assignee: Himax Technologies Limited
    Inventors: Yuan-Kai Chu, Jin-Fu Lin
  • Patent number: 8487705
    Abstract: Embodiments of circuits, apparatuses, and systems for a protection circuit to protect against overdrive or overvoltage conditions. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: July 16, 2013
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Jingshi Yao, Peter Hu, Xiaopeng Sun, Barry Jia-Fu Lin, Mehra Mokalla
  • Patent number: 8487768
    Abstract: Disclosed is an electronic seal for sealing a door. The door is equipped with a latch. The electronic seal includes a plug and a socket. The plug can be inserted in the socket through the latch. Thus, the door is sealed by the electronic seal. The door cannot be opened without breaking the electric seal. The electronic seal records any event of breakage.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 16, 2013
    Assignee: Chung-Shan Institute of Science and Technology, Armaments Bureau, Ministry of National Defense
    Inventors: Ming-Town Lee, Feng-Yu Chang, Tung-Jung Hsu, Chun-Fu Lin
  • Publication number: 20130178063
    Abstract: A method of manufacturing semiconductor device having silicon through via is disclosed, and conductor can be fully filled in the silicon through via. First, a silicon substrate is provided. Then, the silicon substrate is etched to form a through silicon via (TSV), and the through silicon via extends down from a surface of the silicon substrate. Next, a barrier layer is formed on the silicon substrate and in the through silicon via. Then, a seed layer is formed on the barrier layer and in the through silicon via. Afterward, a wet treatment is performed on the seed layer over the silicon substrate and within the through silicon via. The through silicon via is then filled with a conductor.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ling Lin, Chi-Mao Hsu, Tsun-Min Cheng, Jia-Jia Chen, Chin-Fu Lin
  • Patent number: 8481343
    Abstract: A manufacturing method of a molded image sensor packaging structure with a predetermined focal length and the structure using the same are disclosed. The manufacturing method includes: providing a substrate; providing a sensor chip disposed on the substrate; providing a lens module set over the sensing area of the chip to form a semi-finished component; providing a mold that has an upper mold member with a buffer layer; disposing the semi-finished component into the mold to form a mold cavity therebetween; injecting a molding compound into the mold cavity; and after transfer molding the molding compound, opening the mold and performing a post mold cure process to cure the molding compound. The buffer layer can fill the air gap between the upper surface of the lens module and the upper mold member, thereby preventing the upper surface of the lens module from being polluted by the molding compound.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: July 9, 2013
    Assignee: Kingpak Technology Inc.
    Inventors: Chung-Hsien Hsin, Hsiu-Wen Tu, Chun-Hua Chuang, Ren-Long Kuo, Chin-Fu Lin, Young-Houng Shiao
  • Patent number: 8481425
    Abstract: A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: July 9, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yen-Liang Lu, Chun-Ling Lin, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Meng-Hong Tsai
  • Publication number: 20130168744
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Patent number: D688067
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 20, 2013
    Assignee: Whole Space Industries Ltd
    Inventor: Tzong-Fu Lin