Patents by Inventor Fu Lin

Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF FORMING SEMICONDUCTOR DEVICE
    Publication number: 20130045579
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • SHALLOW TRENCH ISOLATION STRUCTURE AND FABRICATING METHOD THEREOF
    Publication number: 20130043513
    Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Liang-An HUANG, Yu-Chun Huang, Chin-Fu Lin, Yu-Ciao Lin, Yu-Chieh Lin, Hsin-Liang Liu, Chun-Hung Cheng, Yuan-Cheng Yang, Yau-Kae Sheu
  • SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH CAPACITOR MISMATCH CALIBRATION AND METHOD THEREOF
    Publication number: 20130044014
    Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventor: Jin-Fu LIN
  • Loop cord tension device for window coverings
    Patent number: 8376022
    Abstract: A loop cord tension device assembly includes a housing, a spring member connected to the housing, a loop cord retention member connected to the housing, and a locking body connected to the spring member. The loop cord retention member has a channel sized and configured to receive a portion of a looped cord. The locking body is moveable from a locked position to an unlocked position. The portion of the loop cord received within the channel of the loop cord retention member is not rotatable when the locking body is in the locked position and the portion of the loop cord received within the channel of the loop cord retention member is rotatable when the locking body is in the unlocked position. The loop cord tension device assembly may be connected to the looped cord of a window covering and mounted to a structure to improve child safety.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 19, 2013
    Assignee: Whole Space Industries Ltd
    Inventor: Tzong-Fu Lin
  • COLOR FILTER ARRAY AND MANUFACTURING METHOD THEREOF
    Publication number: 20130038958
    Abstract: A color filter array includes a substrate, a light shielding layer, and color filter patterns. The light shielding layer is on the substrate and has openings exposing a surface of the substrate. Besides, the light shielding layer has a height H. The color filter patterns are located in the openings of the light shielding layer. Each color filter pattern has the maximum film thickness Lc and the minimum film thickness Ls, and the difference between the maximum film thickness Lc and the minimum film thickness Ls is ?L. The maximum film thickness Lc of each color filter pattern satisfies (m×H)<Lc<(n×H), wherein m comprises about 0.83, n comprises about 0.91, the height H of the light shielding layer satisfies a<H<b, wherein a comprises about 1.6 um and b comprises 2.22 um, and the difference ?L is less than about 0.39 um.
    Type: Application
    Filed: December 7, 2011
    Publication date: February 14, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Shiuan-Fu Lin, Cheng-Yue Lin
  • SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
    Publication number: 20130037886
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Composite contact assembly having lower contact with contact engaging points offset from each other
    Patent number: 8366496
    Abstract: An electrical contact assembly electrical contact assembly comprises upper contact having a lower mating end at a lower end thereof, a lower contact having a base portion and a pair of mating beams extending vertically from the base portion for a length respectively and for engaging with the lower mating end of the upper contact, and a spring located between the upper contact and the lower contact. A channel is defined between the mating beams and providing a space to allow movement of the lower mating end. The pair of mating end has unequal lengths for providing unequal torque on the lower mating end, thus ensuring reliable electrical connection between the upper contact and lower contact even under worse circumstance.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 5, 2013
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Hsiu-Yuan Hsu, Chun-Fu Lin, Shih-Wei Hsiao, Ke-Hao Chen
  • Fin field-effect transistor structure and manufacturing process thereof
    Patent number: 8361854
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 29, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • METAL BUFFER LAYER ASSISTED GUIDED MODE RESONANCE BIOSENSOR
    Publication number: 20130023042
    Abstract: A metal buffer layer assisted guided mode resonance (GMR) biosensor is disclosed. The GMR biosensor includes a substrate, a metal buffer layer and a waveguide layer. The metal buffer layer is disposed on the substrate and the waveguide layer is disposed on the metal buffer layer. The metal buffer layer, which is disposed adjacent to the waveguide layer, can carry out the total reflection and provide extra phase compensation of the total reflection at the same time. Accordingly, the propagation constant of the resonance wave would be much closer to the sensitivity of the phase, and the resonance electric field of the GMR biosensor would be much closer to the sensitive area. Consequently, the sensitivity of the GMR biosensor could be improved.
    Type: Application
    Filed: December 12, 2011
    Publication date: January 24, 2013
    Inventors: Jenq-Yang CHANG, Wen-Yih CHEN, Chih-Cheng CHIEN, Sheng-Fu LIN
  • APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTS
    Publication number: 20130015876
    Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Shi Jordan LAI, Chih-Cheng LU, Yung-Fu LIN, Hsu-Feng HSUEH, Chin-Hao CHANG, Cheng Yen WENG, Manoj M. MHALA
  • ELECTROLYTIC MATERIAL FORMULATION, ELECTROLYTIC MATERIAL COMPOSITION FORMED THEREFROM AND USE THEREOF
    Publication number: 20130010403
    Abstract: An electrolytic material formulation is provided, which comprises: (a1) a conductive compound, (b1) an oxidant and (c1) a polymerizable component. An electrolytic material composition obtained from the electrolytic material formulation through polymerization is also provided. The electrolytic material composition is applicable to a solid capacitor. Compared to a conventional liquid electrolytic capacitor, the solid electrolyte capacitor according to the present invention has advantages of long life, high voltage resistance, high capacitance, and no occurrence of capacitor rupture, and is especially applicable to electronic products that require high temperature resistance and high frequency resistance.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 10, 2013
    Inventors: Shinn-Horng Chen, Chieh-Fu Lin
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20130009288
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20130001707
    Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang, Chan-Lon Yang, Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • TESTING SYSTEM FOR BACKUP BATTERY MODULE OF STORING SYSTEM
    Publication number: 20130007478
    Abstract: A storing system is connected between an external power supply module and a server. The server is connected to external power supply module. The server switches off the external power supply module with the power source when the measured batch file is wholly transmitted to the first storing module. The backup battery module supplies power to the first storing module. The server compares the files stored in the permanent storing module with the measured batch file to determine whether or not the backup battery module is in working order.
    Type: Application
    Filed: September 28, 2011
    Publication date: January 3, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHING-FU LIN
  • Successive approximation register analog-to-digital converter
    Patent number: 8344930
    Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: January 1, 2013
    Assignee: Himax Technologies Limited
    Inventor: Jin-Fu Lin
  • Electrical socket having suitable receiving space for a solder ball of an IC package
    Patent number: 8342873
    Abstract: An electrical socket used to connecting an IC package to a printed circuit board comprises an insulative housing (2) and a plurality of contacts (1) received therein, the insulative housing (2) comprises a top surface (21), a bottom surface (22) opposite to the top surface (21) and a plurality of passageways (211) penetrated the top surface (21) and the bottom surface (22), the contact (1) comprises a body portion (10), a connecting portion (11) extending upwardly from the body portion (10) and a spring portion (12) extending horizontally from the connecting portion (11), the spring portion (12) comprises a supporting portion (120) at the end thereof touching with the insulative housing (2).
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: January 1, 2013
    Assignee: Hon Hai Precision Ind. Co., Ltd
    Inventors: Fang-Jwu Liao, Ke-Hao Chen, Chun-Fu Lin
  • TRANSISTOR HAVING ALUMINUM METAL GATE AND METHOD OF MAKING THE SAME
    Publication number: 20120326243
    Abstract: A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on the substrate. The aluminum metal gate includes a work function tuning layer and an aluminum metal layer disposed orderly on the high-k gate dielectric layer, where the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer. Furthermore, the source/drain region is disposed in the substrate at each of two sides of the aluminum metal gate.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Inventors: Hsin-Fu Huang, Chi-Mao Hsu, Min-Chuan Tsai, Chin-Fu Lin, Chun-Hsien Lin
  • METAL GATE AND FABRICATION METHOD THEREOF
    Publication number: 20120319179
    Abstract: A metal gate includes a substrate, a gate dielectric layer, a work function metal layer, an aluminum nitride layer and a stop layer. The gate dielectric layer is located on the substrate. The work function metal layer is located on the gate dielectric layer. The aluminum nitride layer is located on the work function metal layer. The stop layer is located on the aluminum nitride layer.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Hsin-Fu Huang, Zhi-Cheng Lee, Chi-Mao Hsu, Chin-Fu Lin, Kun-Hsien Lin, Tzung-Ying Lee, Min-Chuan Tsai
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20120319198
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • THROUGH-SILICON VIA FORMING METHOD
    Publication number: 20120322260
    Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien