Abstract: A method for fabricating an interconnection structure includes the following steps. Firstly, a substrate having a first conductive layer thereon is provided. Next, an ultra low-k material layer is formed on the substrate. Next, a portion of the ultra low-k material layer is removed, so as to form an opening to expose the first conductive layer. Next, a dry-cleaning process is performed by using gas, so as to clean a surface of the first conductive layer exposed by the opening. The dry-cleaning process is performed at a temperature in a range from the room temperature to 100° C.

Abstract: An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.

Abstract: A digital apparatus includes a timing control circuit, a period counter, a phase digitizer and a calculation circuit. The timing control circuit generates a first control signal according to a square wave signal and a predetermined value. The period counter generates a first digital value according to a reference clock signal and the first control signal. The phase digitizer generates a second digital value according to a phase difference between the square wave signal and the reference clock signal. The calculation circuit generates an output digital value according to the first digital value and the second digital value. An object of obtaining a high-resolution digitization with a reasonable sampling clock is realized by effectively combining the period counter with the phase digitizer.

Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.

Abstract: A window covering includes a first set of lift cords extending from a headrail to middle rail. The first set of lift cords is extendable between the headrail and the middle rail to a predetermined distance, which defines a lowermost position of the middle rail relative to the headrail. The first set of lift cords is also retractable to a wound position for defining an uppermost position of the middle rail. A second set of lift cords extends from the headrail to the bottom rail and is extendable from between the middle rail and bottom rail to define an extended position of window covering material. The predetermined distance that the first set of lift cords may extend is selected to help prevent children from becoming entangled in the first set of lift cords when the middle rail is lowered away from the headrail.

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.

Abstract: A looped-cord system includes a beaded cord having a set of beads connected in series to form a loop with a space between each pair of adjacent beads. In one embodiment a stop sized to fit within the space between a pair of adjacent beads is attached to a housing. A resilient finger located opposite the stop pushes a portion of the beaded cord adjacent to and not engaging the sprocket against the stop so the stop is within a space between a pair of adjacent beads, thereby preventing movement of the cord loop. Applying tension to the cord loop overcomes the resilient finger and moves the cord away from the stop enabling movement of the cord loop. In another embodiment a key engages the sprocket preventing the sprocket from turning until tension is applied to the cord loop by proper installation of the tensioner on the cord loop.

Abstract: A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.

Abstract: A positioning insert for two adjacent vertebral bodies includes a plate like insert adapted to fix relative positions of the two adjacent vertebral bodies and provided with a sharp edge oppositely formed relative to the dull side and first holes defined through a side face of the plate like insert, wherein the sharp edge is formed to have an angle between 5 to 15 degrees; and an annular insert adapted to be inserted into a space between the two adjacent vertebral bodies and having second holes and a slot defined in a peripheral side face thereof to accommodate the plate like insert so as to have the plate like insert received in the slot.

Abstract: A stage of a pipeline analog-to-digital converter (ADC) is provided according to embodiments of the present invention. The stage of the present invention has double-amplifier architecture and uses level-shifting technique to generate a residue of the stage. The amplifiers of the stage are implemented in two different split paths, thereby to generate a relatively coarse amplification result and a relative fine amplification result. The relatively coarse amplification result is used to level-shift the output level of the amplifier. As a result, the stage of the present invention can have a correct residual by using amplifiers of moderate quality.

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: The present invention discloses an image sensor package structure with a large air cavity. The image sensor package structure includes a substrate, a chip, a cover and a package material. The chip is combined with the substrate. A plastic sheet of the cover is adhered to the chip and a transparent lid of the cover is combined with the plastic sheet to provide a covering over a sensitization area of the chip so as to form an air cavity. The package material is arranged on the substrate and encapsulated around the chip and the cover. The plastic sheet having a predetermined thickness can increase the distance between the transparent lid and the chip to enlarge the air cavity. Thus, the image-sensing effect of the image sensor package structure can be improved and the ghost image problem resulting from multi-refraction and multi-reflection of light can be minimized.

Abstract: A process for producing conjugated diene rubber and its composite includes polymerizing a conjugated diene or a conjugated diene and a vinyl aromatic hydrocarbon in a hydrocarbon solution by anionic polymerization to obtain conjugated diene rubber containing alkali metal in the polymer chain end reacting a with at least one organic silane compound to become a modified conjugated diene rubber. After or during the modified conjugated diene rubber contacting with large amount of water, solvent and water content are removed from the modified conjugated diene by applicable hot sources, wherein coupling ratio of modified conjugated diene rubber is less than 40%, coupling ratio of modified conjugated diene rubber after contact with water is at least 50% The conjugated diene rubber and composite exhibit storage stability.

Abstract: A blind includes a plurality of ladders extending from a headrail. Slats are supported on the ladders. Lift cords extend from the headrail. Each lift cord is adjacent to one of the ladders and extends to the lowermost slat of the slats. Cord shrouds are also included. Each of the cord shrouds enclose a portion of one of the lift cords that extends from the headrail to a position adjacent to the lowermost slat. Each cord shroud is attached to the ladder which is adjacent the lift cord enclosed by the cord shroud. Preferably, each cord shroud is either a rail of the ladder or is otherwise attached to a ladder at spaced apart locations to prevent the lift cord enclosed by the cord shroud from being pulled away from the slats to form a loop of a size capable of posing a danger to a small child.

Abstract: Disclosed is an electronic seal for sealing a door. The door is equipped with a latch. The electronic seal includes a plug and a socket. The plug can be inserted in the socket through the latch. Thus, the door is sealed by the electronic seal. The door cannot be opened without breaking the electric seal. The electronic seal records any event of breakage.

Abstract: An integrated circuit with a flexible data strobe signal (DQS) bus structure is presented. The integrated circuit has a number of input/output (I/O) modules with a number of data pins to receive and transmit data. In addition, a subset of the I/O modules also have a data strobe pin. The input/output modules are connected to data strobe signal buses having a fixed configuration. The configuration of the fixed DQS bus groups a number of data pins with a corresponding data strobe pin and the grouping of data pin spans multiple I/O modules. The integrated circuit also has a flexible data bus connected to the I/O modules. Data pins of I/O modules of a second integrated circuit are mapped a subset of the data pins of corresponding I/O modules of the integrated circuit. The flexible data strobe signal bus enables selection of the subset of data pins in the integrated circuit.

Abstract: The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz.