Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

Abstract: A high-speed connector includes an insulating housing, and a first terminal assembly mounted in the insulating housing. The first terminal assembly includes a plurality of first terminals including a plurality of first grounding terminals, a first base body, and a first shielding plate disposed under the first base body. The plurality of the first terminals are fastened to the first base body. The first shielding plate has a first base plate, a first metal layer and a plurality of first ribs. Several portions of a top surface of the first base plate extend upward to form the plurality of the first ribs. The first metal layer is a pattern with a plurality of pores. Several of the first grounding terminals contact with the first metal layer which is attached to top surfaces of the plurality of the first ribs to form a grounding structure.

Abstract: A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The method includes providing a first metal layer defining a first slot; forming a first adhesive layer in the first slot; electroplating copper on each first pillar to form a first heat conducting portion; forming a first insulating layer on the first adhesive layer having the first heat conducting portion, and defining a first blind hole in the first insulating layer; filling the first blind hole with thermoelectric separation metal to form a second heat conducting portion; forming a first wiring layer on the first insulating layer; forming a second insulating layer on the first wiring layer, defining a second blind hole on the second insulating layer; electroplating copper in the second blind hole to form a third heat conducting portion; mounting an electronic component on the second insulating layer.

Abstract: An electrical connector includes an insulating body, a plurality of terminals fastened in the insulating body, an elastic element mounted to a surface of the insulating body, a camshaft and a shell. The elastic element has a body portion, at least one elastic arm slantwise extended frontward and outward, and then extended frontward from one end of the body portion, at least one extension arm slantwise extended outward and rearward from at least one side of the body portion, and a tail portion slantwise extended upward and rearward from the other end of the body portion. The camshaft is arranged at a rear end of the insulating body. The camshaft has a rotating shaft and a cam portion. The cam portion is arranged corresponding to the tail portion. The shell surrounds the insulating body, the plurality of the terminals, the elastic element and the camshaft.

Abstract: A semiconductor structure, including a substrate and multiple chips, is provided. The chips are stacked on the substrate. Each of the chips has a first side and a second side opposite to each other. Each of the chips includes a transistor adjacent to the first side and a storage node adjacent to the second side. Two adjacent chips are bonded to each other. The transistor of one of the two adjacent chips is electrically connected to the storage node of the other one of the two adjacent chips to form a memory cell.

Abstract: An electronic package, in which a heat dissipation structure is disposed on a carrier structure to form a packaging space for electronic components to be accommodated in the packaging space, and the electronic components are completely encapsulated by a heat dissipation material to prevent the electronic components exposing from the heat dissipation material so as to improve the heat dissipation effect.

Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.

Abstract: A wireless radio frequency conversion system is disclosed. The wireless radio frequency conversion system includes a wireless radio frequency transmit-receive device, a first conversion device, at least one optical fiber, a second conversion device, and a wireless radio frequency transmission device. The wireless radio frequency transmit-receive device performs a conversion and a transmit-receive manner to at least one radio frequency signal and at least one data signal. The first conversion device performs a conversion to the at least one data signal and at least one optical signal. The optical fiber transmits the at least one optical signal. The second conversion device performs a conversion to the at least one optical signal and the at least one data signal. The wireless radio frequency transmission device performs a conversion and a transmit-receive manner to the at least one data signal and the at least one terminal signal.

Abstract: The present invention provides a method of controlling a display panel. The display panel includes a plurality of subpixels and a plurality of scan lines coupled to the plurality of subpixels. The method includes steps of: scanning a first scan line among the plurality of scan lines to turn on at least one of the plurality of subpixels coupled to the first scan line during a subframe period among a display frame period; and discharging a second scan line among the plurality of scan lines during a non-display period following the subframe period. Wherein, the second scan line is different from the first scan line.

Abstract: A system comprises a memory storage configured to store at least a portion of a frame of a video and a hardware motion estimation search processing unit configured to perform at least a portion of a motion estimation search for the video for a plurality of different block sizes. The hardware motion estimation search processing unit is configured to perform the motion estimation search using a plurality of source sub-blocks of a first block size to determine a first type of comparison evaluation values for the first block size. A combination of values included in the first type of comparison evaluation values is utilized to determine at least one second type of comparison evaluation values for a second block size, wherein the second block size is larger than the first block size.

Abstract: The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure, wherein the opening overlies at least a portion of the semiconductor device.

Abstract: A method of identifying a location of pathogens in a structure including monitoring air within the structure for pathogens to set a baseline level, detecting a rise in pathogen density with respect to the baseline level, at least partially closing at least a first zone of the system, monitoring air from a second zone for a change in relative pathogen density to the previously detected pathogen density, and toggling the first zone and the second zone based on the change in relative pathogen density.

Abstract: A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The method includes providing a first metal layer defining a first slot; forming a first adhesive layer in the first slot; electroplating copper on each first pillar to form a first heat conducting portion; forming a first insulating layer on the first adhesive layer having the first heat conducting portion, and defining a first blind hole in the first insulating layer; filling the first blind hole with thermoelectric separation metal to form a second heat conducting portion; forming a first wiring layer on the first insulating layer; forming a second insulating layer on the first wiring layer, defining a second blind hole on the second insulating layer; electroplating copper in the second blind hole to form a third heat conducting portion; mounting an electronic component on the second insulating layer.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: A torque output device includes a body with an opening in the top. A top toothed part is located beneath the opening and includes a bore located corresponding to the opening. The top toothed part includes multiple top teeth. A drive shaft secured in the body and includes a central hole in which a rod is located. A driving portion is formed to the lower end of the drive shaft. The drive shaft and the top toothed part are freely rotated relative to each other. A bottom toothed part is mounted to the drive shaft and freely moves up and down relative to the drive shaft. A resilient member is mounted to the drive shaft and biases the bottom toothed part. A pressure collar is threadedly connected to the lower end of the body to set the torque between the engagement of the top and bottom teeth.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a well region disposed within a semiconductor substrate and comprises a first doping type. A gate electrode overlies the well region. A first contact region is disposed within the well region and comprises a second doping type opposite the first doping type. A second contact region is disposed within the semiconductor substrate and laterally offset from the well region. The second contact region comprises the first doping type and the gate electrode is disposed between the first contact region and the second contact region. A gate dielectric layer is disposed between the semiconductor substrate and the well region, where a thickness of the gate dielectric layer is greater than about 140 Angstroms.

Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.