Abstract: An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.

Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Abstract: An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

Abstract: An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.

Abstract: A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively.

Abstract: A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate.

Abstract: A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.

Abstract: A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set of plugs are coupled together as a first resistor segment to provide a predetermined resistance for the integrated circuit.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: An integrated circuit structure includes an image sensor cell, which further includes a photo transistor configured to sense light and to generate a current from the light.

Abstract: A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively.

Abstract: A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

Abstract: A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.

Abstract: A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.

Abstract: Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.

Abstract: Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated.

Abstract: A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.

Abstract: Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated.